Post-synthèse simulation

[molka]

Hello,

I want to run a post-synthesis simulation. I don't find where to
choose the sources (Netlist post-synthesis) to launch the needed
simulation from ISE 13.3.

Does someone know how to do it ? I need some help.

Simulator: ModelSim SE-64 10.0d
Xilinx tools: 13.3

Molka
PhD student

[maxascent]

Why do you want to do this? I have never had a reason to do this and my
designs have all worked just fine. Just do a behavioural sim and ensure
your design passes timing and you will be ok.

Jon

---------------------------------------
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[Joel Williams]

>> I want to run a post-synthesis simulation. I don't find where to
>> choose the sources (Netlist post-synthesis) to launch the needed
>> simulation from ISE 13.3.
>>
>> Does someone know how to do it ? I need some help.
>>
>> Simulator: ModelSim SE-64 10.0d
>> Xilinx tools: 13.3
>>
>> Molka
>> PhD student
>>
>
> Why do you want to do this? I have never had a reason to do this and my
> designs have all worked just fine. Just do a behavioural sim and ensure
> your design passes timing and you will be ok.

One scenario that comes to mind is to avoid annoying problems where the
behavioural models are broken. See this thread about the Xilinx FIFO core:

http://forums.xilinx.com/t5/Simulation-and-Verification/Spartan-6-FIFO-problem-in-13-1/td-p/154690

Joel

[Andy]

On Jan 29, 9:36 am, "maxascent"

I would qualify that you should run full simulations on RTL, run STA
with complete and accurate timing constraints on the design, and then
run a subset of your simulation post-P&R. If you have any non-timing
issues PPR, then you might try a post-synthesis simulation to isolate
the problem to synthesis or P&R. One of the issues not caught by
behavioral simulation plus STA is the accuracy of false- and multi-
cycle-path constraints. If you use these in STA, they need to be
verified by PPR simulation.

Andy

[RCIngham]

The correct workaround for this problem is to generate Structural FIFO
models, and use them in your pre-synthesis simulations. AFAIK, all the
Behavioural FIFO models are broken.

I can think of other reasons to do post-PAR simulations, for instance if
you have a tricksy start-up sequence involving multiple clocks.

[guenter]

From within ISE13.3's Project Manager, having a VHDL project:
Select the "Design" tab
In the Hierarchy pane (upper area) select the top-level unit of your
design
In the Processes pane (lower area), expand "Synthesize - XST" and
double-click on "Generate Post Synthesis Simulation Model"
This generates a folder within your project named netgen/synthesis and
within this folder, there is a file named <top>_synthesis, where <top> is
the name of your project's top level VHDL file.
This file must be compiled with ModelSim, together with your testbench.
I'm not sure what is necessary to launch ModelSim directly from ISE,
because I'm always using separate scripts for ModelSim.

regards
Guenter