Virtex 5 bitstream encryption

[bambout...@hotmail.com]

Hello !
I would like to know the frequency used by Xilinx (Virtex 5) to
decrypt bitstream before configuration .
The decrypter is it slow with small area ? fast with big area ?
unfortunately it's not documented by xilinx .

Thank u for help

[Peter Alfke]

Do you mean ENcrypt when you wrote DEcrypt ?
Peter Alfke

[bambout...@hotmail.com]

Peter ,
i mean "decrypt ", in fact encrypted bitstream is sent from Eprom to
Fpga to be decrypted then configured . i want to know more about this
decrypter . which AES 256 decryption architecture is used by xilinx
( area , throughput , ...) .

[Ed McGettigan]

It decrypts at the same rate as the configuration clock. This could be
anywhere from KHz to the maximum of 100 MHz as specified in the data sheet.

Ed McGettigan
--
Xilinx Inc.

[bambout...@hotmail.com]

On 27 août, 18:29, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

Ed ,
thank for you answer .
The rate of config clk is fixed by the user ( from 2Mhz to 60Mhz ) so
i did not understand by "anywhere from KHz to the maximum of 100
MHz" , moreover with my
encrypted bitstream (Eprom => FPGA) i couldn't run over 42 Mhz .
why ?
What i want to know is the throughput of the decrypter (AES 256 CBC) ,
how many cycles takes this architecture used by Xilinx ? is it Safe
at 100% against attacks ( timing , fault attack , side channel
attack ....) ?
thank u

[Ed McGettigan]

bambout...@hotmail.com wrote:
> On 27 août, 18:29, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>> bamboutcha9...@hotmail.com wrote:
>>> Hello !
>>> I would like to know the frequency used by Xilinx (Virtex 5) to
>>> decrypt bitstream before configuration .
>>> The decrypter is it slow with small area ? fast with big area ?
>>> unfortunately it's not documented by xilinx .
>>> Thank u for help
>> It decrypts at the same rate as the configuration clock. This could be
>> anywhere from KHz to the maximum of 100 MHz as specified in the data sheet.
>>
>> Ed McGettigan
>> --
>> Xilinx Inc.
>
>
> Ed ,
> thank for you answer .
> The rate of config clk is fixed by the user ( from 2Mhz to 60Mhz ) so
> i did not understand by "anywhere from KHz to the maximum of 100
> MHz" ,

2 MHz to 60 MHz falls within the window that I stated of KHz to 100 MHz.

> moreover with my
> encrypted bitstream (Eprom => FPGA) i couldn't run over 42 Mhz .
> why ?

Likely because of the timing relationships created by the EPROM. You
should review the data sheet for the EPROM to verify the maximum
frequency of operation in the mode that you are using it.

> What i want to know is the throughput of the decrypter (AES 256 CBC) ,
> how many cycles takes this architecture used by Xilinx ?

The decrypter input-to-output is 1:1, so there are no stalls required
for the input bitstream. I don't know what the latency is of the actual
block as it has no impact on the configuration sequence.

> is it Safe
> at 100% against attacks ( timing , fault attack , side channel
> attack ....) ?

Austin Lesea has said once or twice in this newsgroup that the NSA has
approved it as secure and we know of no one that has broken it.