FPGA + ASIC: generate signals and readout
Konx
I have the following situation, it is a bit complicated to explain but
I hope I can make myself clear.
- I have a board (called S1) with an FPGA on it, and other stuff
(microcontroller, many connectors, memory, etc...). The only thing I
think it is useful to know for you, is that I have access to the FPGA
via USB cable.
- In another board (called S2) I have an ASIC chip to test.
At the present time, I'm able to load a simple bitstream (generated
using Xilinx ISE environment) on the FPGA. I can load this bitstream
because someone wrote a simple driver to control the FPGA, so I can
just start the program, press a "browse" button to select the
bitstream and press the "upload" button to load the bitstream.
In the next days, I have to write a simple Verilog code to provide
signals to the FPGA (like token, trigger, etc...not important).
Given these signals, the chip has to perform some operation, and it
gives me an output. The output is a serial data of 48 bit.
Here start the problems:
- I have to store the data somewhere in the FPGA, so I was thinking
that I could create some RAM (using the Core Generator for example)
and then store the data inside these kind of register.
- Then, I have to read out the FPGA. To do this, I have a C++ header
file with some functions in it, that I can use to read out the data.
Questions:
- do you think that the RAM solutions is ok? are there any better ways
to store the data?
- is there another way to read out the chip? I mean, suppose I don't
have the C++ functions, is it still possible to read the data arriving
at a certain pin of the FPGA? I think it should be possible, but at
the moment I have no idea how to do this. Moreover, I need to store
these data in a file...I guess this should be possible too.
I know that the problem is quite general but if you could give me some
guidelines I would really appreciate it, so at least I know what I
have to search for.
Thank you for any help
Francesco.