webpack ISE synthesis fails with exit code: 0002

[Eric Smith]

I'm trying to use WebPACK ISE to build a microprocessor core model
using an XC2S200. I can't get the data path to compile; the synthesizer
exits with the message:

Done: failed with exit code: 0002.

I don't think I'm doing anything too strange. I did have to change it
somewhat from the design I was using with the Cypress tools, because
I used ieee.numeric_std with those.

I stripped down the data path until all that is left is the adder,
and I still get the error. While it's entirely possible that I've
screwed something up and this may not be a legal VHDL file, I'm
astonished that the synthesizer would exit with a non-zero exit code
without actually telling me what it is upset about.

Here's the code:

library ieee;
use ieee.std_logic_1164.all;
entity adder is
port (
carry_in : in std_logic;
a, b: in std_logic_vector (7 downto 0);
result: out std_logic_vector (7 downto 0);
carry_out_4: out std_logic; -- digit carry
carry_out_8: out std_logic; -- the "real" carry out
overflow: out std_logic -- two's complement overflow
);
end adder;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
architecture arch_adder of adder is
signal sum_low : std_logic_vector (4 downto 0);
signal sum_high : std_logic_vector (9 downto 4);

begin
sum_low <= (('0' & a (3 downto 0)) + ('0' & b (3 downto 0))) + carry_in;
sum_high <= (('0' & (a (7) & a (7 downto 4))) +
('0' & (b (7) & b (6 downto 4)))) + sum_low (4);

result <= sum_high (7 downto 4) & sum_low (3 downto 0);
carry_out_4 <= sum_low (4);
carry_out_8 <= sum_high (9);
overflow <= sum_high (8) xor sum_high (7);

end architecture arch_adder;

The .plg file is below. Anyone have any ideas as to what's going wrong?
Can anyone else reproduce the problem?

I'm using Design Entry 3.2WP3.1, Spartan 2 fitter 3.2WP3.2, and JTAG
programmer 3.2WP3.1. I've successfully compiled the ledflash example
that Burch Electronic Designs provides as a demo of their BED-SPARTAN2+
board, so I think WebPACK is installed correctly.

Thanks!
Eric

=========================================================================
---- Global Settings
Tmp directory : .
DUMPDIR : .
overwrite : YES

=========================================================================

XST D.22
Copyright (c) 1995-2000 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to .

--> Parameter DUMPDIR set to .

--> Parameter overwrite set to YES

--> =========================================================================
---- Source Parameters
Input File Name : adder.prj
Input Format : VHDL

---- Target Parameters
Output File Name : adder.edn
Output Format : EDIF

---- Source Options
Entity Name : adder
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
HDL Verbose Level : 1
RAM Extraction : Yes
RAM Style : Auto
Mux Extraction : YES
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
Resource Sharing : YES
Complex Clock Enable Extraction : YES
Resolution Style : WIRE_MS

---- FSM Options
FSM Flip-Flop Type : D

---- Target Options
Family : Xilinx_Virtex
Device : 2S200-PQ208-5
Macro Generator : Macro+
Add IO Buffers : YES
Add Generic Clock Buffer(BUFG) : 4
Global Maximum Fanout : 100
Keep Hierarchy : NO

---- General Options
Optimization Criterion : Speed
Optimization Effort : 1
Global Optimization : AllClockNets
Incremental Synthesis : NO

=========================================================================

Compiling vhdl file C:\Xilinx_WebPACK\data\webpack\genff.vhd in Library genff.
Entity <g_depc> (Architecture <behavioral>) compiled.
Entity <g_tpc> (Architecture <behavioral>) compiled.
Entity <g_latpc> (Architecture <behavioral>) compiled.
Compiling vhdl file E:\xproj\adder\adder.vhd in Library work.
Compiling vhdl file E:\xproj\adder\adder_arch.vhd in Library work.
Entity <adder> (Architecture <arch_adder>) compiled.

Analyzing Entity <adder> (Architecture <arch_adder>).
Entity <adder> analyzed. Unit <adder> generated.

Synthesizing Unit <adder>.
Extracting 4-bit adder carry in/out for signal <sum_low<3:0>>.
Extracting 5-bit adder carry in/out for signal <sum_high<4:0>>.
Extracting 1-bit xor2 for signal <overflow>.

[Eric Smith]

"S. Ramirez" <sram...@deletethis.cfl.rr.com> writes:
> Since you were brilliant enough to include the code and make it easy, I
> copied the code into a file and ran it through Synplify 6.1.3/Design Manager
> 3.3.06i.
> I targeted a Spartan 2 chip, and everything ran fine. In other words,
> the Synplify tool did not detect any errors and pumped out an EDIF file
> correctly.

Thanks for verifying that my code is OK. Or at least OK enough to please
other synthesizers.

> I would immediately start suspecting the XST tools, which are
> fairly new and I suspect "bug-not-free."

I suspected that to be the case. I've tried a few ways to restructure
the code, and so far I have not been able to figure out specifically
what about my code is making XST unhappy.

Maybe someone from Xilinx will try it. I suppose I should figure out how
to submit a bug report.

> If you want, you can email me your
> entire code, and I will run it through the Synplify tool and ship you back
> an EDIF file.

Thanks for the kind offer, but I don't think it would make much sense
to do that just yet. I'm still developing the uP core. I was originally
targetting a Cypress CY37512 CPLD, but I ran out of routing resources.
This forced me to split my design explicitly into control and data path
sections, which I think is architecturally better anyhow. After the split
I was targetting the pieces to a CY37256 and a CY37512. It looks like it
will fit.

However, the Spartan II parts look more cost effective. Originally I
avoided them because:

1) The Xilinx software was too expensive, I am doing this as
self-education and didn't have any budget for expensive tools.
Xilinx fixed this with the introduction of the WebPACK ISE.

2) The Spartan II parts availability was poor. This is improving,
but for me the big break was finding out about the cheap (US $120)
XC2S200 eval board from www.burched.com.

It looks like my design should run much faster in the XC2S200-5 than
in the Cypress CPLDs, because in the latter I had five levels of
feedback in the data path.

Once my model is complete and at verified, I'll make it publicly
available.

Best regards,
Eric

[Andy Peters noao [.] edu>]

Eric Smith wrote:
>
> I'm trying to use WebPACK ISE to build a microprocessor core model
> using an XC2S200. I can't get the data path to compile; the synthesizer
> exits with the message:
>
> Done: failed with exit code: 0002.

Just a guess, 'cause I'm not sure...but does the Webpack stuff support
that particular part?

-a

[Eric Smith]

I wrote:
> I'm trying to use WebPACK ISE to build a microprocessor core model
> using an XC2S200. I can't get the data path to compile; the synthesizer
> exits with the message:
>
> Done: failed with exit code: 0002.

Andy Peters <"apeters <"@> noao [.] edu> writes:
> Just a guess, 'cause I'm not sure...but does the Webpack stuff support
> that particular part?

Yes. That's the only part I have an eval board for, so it's the only
part I've targetted. The simple LED-flasher design worked fine.