Xilinx IOB flip flop mapping
Jake Janovetz
It's been a long time since I've posted here. Seems like forever.
I'm having a bear of a time trying to get a particular design to map
IOB FFs to registered outputs and was hoping someone here could help.
I've read several items found in Xilinx answers and technical
documentation and it's not working. I would prefer not to explicitly
instantiate the IOB FF in my Verilog, but it may be the next step.
I've turned on IOB FF mapping in XST (it's on auto by default).
Essentially, my code is:
-----
reg [7:0] something, other;
wire [7:0] outputsomethingorother;
reg [7:0] outputbus;
assign outputsomethingorother = which ? something : other;
always @(posedge clk) begin
outputbus <= outputsomethingorother;
end
-----
'something' and 'other' should become internal CLB FFs.
'somethingorother' should become the output of a CLB MUX. 'outputbus'
should become a bunch of IOB FFs, right?
Jake
Duane Clark
> Hi folks...
>
> It's been a long time since I've posted here. Seems like forever.
> I'm having a bear of a time trying to get a particular design to map
> IOB FFs to registered outputs and was hoping someone here could help.
>
> I've read several items found in Xilinx answers and technical
> documentation and it's not working. I would prefer not to explicitly
> instantiate the IOB FF in my Verilog, but it may be the next step.
> I've turned on IOB FF mapping in XST (it's on auto by default).
> Essentially, my code is:
There are two places where the mapping has to be turned on. The first is
in the synthesis properties, which you already have. The second is in
the "Process Properties", where you need to select the tab "Map Properties".
--
My real email is akamail.com@dclark (or something like that).
Jake Janovetz
Thanks... I checked and it was set to "For Inputs and Outputs". I
also tried instantiating a "FD" element. Still no luck. The element
gets mapped to a DFF, but not inside an IOB.
Any ideas?
Jake
Duane Clark <junk...@junkmail.com> wrote in message news:<b74gb...@enews1.newsguy.com>...
Kevin Brace
You are not the only one having a problem with Xilinx IOB.
While back, I also had problems with it, and took about two weeks to
figure out XST to duplicate FFs.
The thing about an IOB FF is that, unless the fan out coming out of the
FF is one (1), the FF won't be pushed into the IOB.
If you are not seeing the FFs getting pushed into IOBs, very likely the
fan out coming out is not one.
To see the fan out coming out of a FF, look at an EDIF netlist generated
by the synthesis tool, however, when ISE 4.1 was released, Xilinx
"officially" dropped EDIF netlist generation capability from XST.
But after some experiments, I found a way to get XST to generate an EDIF
netlist, and these two postings explain how to do it.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=aceeac%249fj%241%40newsreader.mailgate.org
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=ad2sbv%248u0%2401%241%40news.t-online.com
After you figure out the FF fan out issue, read this posting,
and follow the instructions I wrote.
I hope the instructions are helpful, and let me know if it
worked or not.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Uwe Bonnes
: Jake,
: You are not the only one having a problem with Xilinx IOB.
One thing that is missleading in the data sheet is the polarity of the
Tristate Output Buffer enable. While it is shown "active high " in the data
sheets, it is "active low" in reality. So with al the other prerequisits
set, a verilog expression like
inout [7:0] busdata;
wire busenable;
wire [7:0] outdata;
assign busdata = (busenable)? outdata: 8'bz;
doesn't get pushed into the IOBs, but
assign busdata = (!busenable)? 8'bz: outdata;
_gets_ pushed into the IOBs.
It took me some time to find out. A request to clarify the data sheets is
pending...
Bye
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Jake Janovetz
I'll look at this possibility. I found _my_ err, though. Since I
don't have the FPGA editor for a little while (offsite, using the
Webpack), I was trying to use the floorplanner information to
determine if something was pushed to the IOB by looking at the IOB pin
mappings. It doesn't appear that this is a valid method to determine
IOB packing.
Does anyone have any suggestions on how else to see if a FF is inside
the IOB? I'm going to try Kevin's EDIF output, but wouldn't expect
that to tell me. I definitely only have a fanout of 1. My test case
while I play with this is IPAD -> FF -> OPAD. Pretty basic.
Cheers,
Jake
Uwe Bonnes <b...@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<b75t3g$3ao$1...@news.tu-darmstadt.de>...
Phil Hays
> Does anyone have any suggestions on how else to see if a FF is inside
> the IOB?
Set offset timing constraint in the ucf file that will fail unless the
FF is inside the IOB.
--
Phil Hays
Kevin Brace
Jake Janovetz wrote:
>
> Thanks, Uwe-
>
> I'll look at this possibility. I found _my_ err, though. Since I
> don't have the FPGA editor for a little while (offsite, using the
> Webpack), I was trying to use the floorplanner information to
> determine if something was pushed to the IOB by looking at the IOB pin
> mappings. It doesn't appear that this is a valid method to determine
> IOB packing.
>
Jake, you can also read a report generated by MAP to see if FFs
were indeed pushed into the IOB.
That way you don't have to P&R, which saves time.
Kevin Brace
I once complained about the tri-state buffer polarity to Peter Alfke of
Xilinx, and he told me that Xilinx's tri-state buffer is active high
tri-state, so the datasheet is actually correct.
In other words, active high tri-state means that the tri-state buffer is
active low enable.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)