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Using both Verilog and VHDL for Xilinx simulation
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Michael
Feb 21, 2012, 4:43:57 PM2/21/12
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Hi,
How do I setup synopsys_sim.setup for simulating both Verilog and VHDL
using VCS for a Xilinx FPGA?
I need for instance have SIMPRIM point to both the VHDL and the Verilog
compiled library path, I did try using a : and simply append them but it
failed.
/michael
How do I setup synopsys_sim.setup for simulating both Verilog and VHDL
using VCS for a Xilinx FPGA?
I need for instance have SIMPRIM point to both the VHDL and the Verilog
compiled library path, I did try using a : and simply append them but it
failed.
/michael
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