clock divider by 1.5

[Goran]

Im beginer in vhdl and i need to create a clock divider by 1.5.I have found such one in edn magazine (on the web) but it didnt help me.Does someone have better idea then the one in edn magsine.

If someone wants to look at the design in edn : http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htm

[Peter Alfke]

You have two different choices:

If your incoming clock has a 50% duty cycle, just use both edges, as described in
http://www.xilinx.com/xcell/xl33/xl33_30.pdf

If   you don't want to trust the duty cycle, you must first double the clock frequency, then divide by 3.
All Virtex devices have a clock-frequency doubler in their DLL, so the solution is trivial.

Peter Alfke, Xilinx Applications
========================

[Alex Gaivoronsky]

Just idea.
You can use booth rising and falling edges from master clock. You need
to build clock doubler - just use exclusive or with clock, and delayed
clock. Then just divide by 3.

Alexander
Goran <goran_...@yahoo.com> wrote in message
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[Wolfgang Loewer]

Goran,

you might want to take a look at Alteras APEX 20KE architecture. These
devices have on-chip PLLs, that allow to multiply incoming clocks by
m/(n*k). With the Altera Megawizard you would paramterize your PLL and
generate a black box which you could then put into your clock path by
instantiating it within your VHDL code.
It's usualy better design technique to use something like a PLL rather than
combinatorial, asynchronous logic or even combinatorial feedback loops
within a clock path.

Regards
Wolfgang

Goran <goran_...@yahoo.com> wrote in message
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[Utku Ozcan]

Goran wrote:

> Im beginer in vhdl and i need to create a clock divider by 1.5.I have found such one in edn magazine (on the web) but it didnt help me.Does someone have better idea then the one in edn magsine.
>
> If someone wants to look at the design in edn : http://www.ednmag.com/ednmag/reg/1996/101096/21di_05.htm

Peter Alfke from Xilinx has an clock divide by 1.5
implementation in Xilinx technology:
http://www.xilinx.com/xcell/xl33/xl33_30.pdf

Utku

[goran]

first thank you all for taking time to help me and second :clock divider i found in the article didnt wok so good maybe it is becouse im using a xc4k device.i thought to make a clock multiplier (all multipliers use some sort of delay) but i dont have a dll in my libraries (im using xilinx foundation to make designs).if someone has some other idea or can help me with this please do so .(i need to extract 1.08mhz clock from 12.15mhz one)

[Ray Andraka]

You can use direct digital synthesis to get a 1.08 MHz clock from an 12.15 MHz
one. It will have jitter up to one cycle time of the 12.15 MHz clock on it. T
oreduce the jitter use a faster master clock. For details on the direct digital
synthesis, look back in this newsgroups archives in deja news for DDFS or direct
digital synthesis. It has been discussed here many times.

goran wrote:
>
> first thank you all for taking time to help me and second :clock divider i found in the article didnt wok so good maybe it is becouse im using a xc4k device.i thought to make a clock multiplier (all multipliers use some sort of delay) but i dont have a dll in my libraries (im using xilinx foundation to make designs).if someone has some other idea or can help me with this please do so .(i need to extract 1.08mhz clock from 12.15mhz one)

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com or http://www.fpga-guru.com

[Bertram Geiger]

goran schrieb:

>
> first thank you all for taking time to help me and second :clock divider i found in the article didnt wok so good maybe it is becouse im using a xc4k device.i thought to make a clock multiplier (all multipliers use some sort of delay) but i dont have a dll in my libraries (im using xilinx foundation to make designs).if someone has some other idea or can help me with this please do so .(i need to extract 1.08mhz clock from 12.15mhz one)

Did i miss something ? I understood that you first asked for a divider
by 1.5
The above is a divider by 11.25 or by 45/4
That results in a modulo 45 counter, incremented by 4 with every cycle

Bertram

--
Bertram Geiger, bge...@aon.at
HTL Bulme Graz-Goesting - AUSTRIA

[goran]

to bertram geiger
You are wright about clock but it is not the only clock i need to extract so i thought to do it by dividing in couple segments so that it will be easier to get other clocks.As i wrote earlier im novice in vhdl so if you can help me with mod counter i will be thankfull.(im learning while working so all information is more than wellcome)