FPGA decoupling calculation
kislo
decoupling network for a spartan3e 500k (powered by the triple power
supply from texas instruments TPS75003) .. i dont have the luxury of a
software tool to help me simulate and analyse, but i just want a good
estimate which can be supported by theoretic statements. I have read
xapp623 (Power Distribution System (PDS) Design), and calculated the
number and values of capacitors using the method in the application
node. This is the results:
Vccint - 1.2V 8 supply pins
1 - 4,7uF
2 - 0.47uF
5 - 0.047uF
Vccaux - 2.5V 8 supply pins
1 - 4,7uF
2 - 0.47uF
5 - 0.047uF
Vcco - 3.3V 14 supply pins
1 - 10uF
2 - 4.7uF
4 - 0.47uF
8 - 0.047uF
So here i start wondering ... the application node method is to have
one capacitor per vcc/gnd pin ... according to my knowledge (probably
bad), the decoupling capacitors should be determined from the
(frequency dependent)dynamic current requirement of the fpga. Since im
designing the decoupling network for a unknown fpga utialization i am
only interrested in the worst case scenario. If we take Vccint for
example:
1.2V 5% tolerance - 2A max - 0.5ns risetimes
Inorder for the voltage ripple to be under 5% for the bandwidth of
0.35/0.5ns = 700Mhz, the impedance of the PDS must be below :
(1.2V*0.05)/2A = 0.03R
Inorder for this to be realised i need INSANLY many decoupling
capacitors. By placing 14 0.0047uF, 10 0.047uF, 2 0.47uF I can stay
below 0.03R for a 80Mhz bandwith .... that means i still need to cover
up to 700Mhz :/ .. but this result is far from what result i got from
the xilinx application note ..
I know that the previous calculations assumed that the current demand
for the harmonics were 2A for the entire bandwidth, but how does the
current relate to the harmonics of a signal transitions? if i got
50Mhz swiching frequency will the current drop with 20db/decade, just
as the amplitude of the harmonics?
regards kim
Symon
I've not got much time so here's a few pointers:-
IMO, Xilinx publish excessive requirements which covers their arse if
anything should go wrong. Fair enough. However, you should know that it's
fairly difficult to get this wrong, indeed, some folks (not me!) on this
newsgroup apparently use very few bypass caps.
Free capacitor parameter stuff.:-
http://www.murata.com/designlib/mcsil/index.html
Above a few 10's of MHz, all same sized caps have the same impedance. (See
murata thing above) Just use 0402 1uF for everything. One per pin is more
than enough. Make sure your board has a ground plane, try to use two vias
for each cap terminal.
Here's some stuff on where to place your caps.
http://www.sigcon.com/pubsIndex.htm#bypass%20capacitors
Or, ignore that stuff, sooo 20th C. Better bypass here:-
http://www.x2y.com/
Finally, there are caps hidden in the FPGAs themselves. Go to your
university's chemistry dept. and ask for some HF to find them!
Also, STFW ! ;-)
HTH, Syms.
Uwe Bonnes
> IMO, Xilinx publish excessive requirements which covers their arse if
> anything should go wrong. Fair enough. However, you should know that it's
> fairly difficult to get this wrong, indeed, some folks (not me!) on this
> newsgroup apparently use very few bypass caps.
If you route the Xilinx recommended number of CAPs, you either have no room
for signal breakout or the bypass caps end up far away from the FPGA. The
calculation also seems to forget about the interinsic C and L of the supply
layers.
My rule is: - try to implement a good ground plain, no swiss cheese
- try to place one 0603/0402 cap in X5/7R near each supply pin
with the traces to the FPGA as short as possible
--
Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Symon
news:fn4int$d1c$1...@lnx107.hrz.tu-darmstadt.de...
> Symon <symon_...@hotmail.com> wrote:
>> Hi Kim,
>> I've not got much time so here's a few pointers:-
>
>> IMO, Xilinx publish excessive requirements which covers their arse if
>> anything should go wrong. Fair enough. However, you should know that it's
>> fairly difficult to get this wrong, indeed, some folks (not me!) on this
>> newsgroup apparently use very few bypass caps.
>
> If you route the Xilinx recommended number of CAPs, you either have no
> room
> for signal breakout or the bypass caps end up far away from the FPGA. The
> calculation also seems to forget about the interinsic C and L of the
> supply
> layers.
>
Indeed. I notice their own dev. boards don't follow the XAPP recomendation.
Hmmm.
Cheers, Syms.
Allan Herriman
<kis...@student.sdu.dk> wrote:
>... decoupling network ...
> .. i dont have the luxury of a software tool to help me simulate and analyse
The headers in your post suggest you are using Windows. That's good,
because you can download LTSpice and use that.
http://www.linear.com/designtools/software/switchercad.jsp
Like all simulations, the results are only as good as your models. In
particular, you'll end up with lumped approximations which may result
in resonances that don't appear on the real board.
(The real board will have distributed capacitance, and also dielectric
loss (which gets rid of a lot of the impedance peaks).)
Regards,
Allan
kislo
>
> - Vis tekst i anførselstegn -
yea i noticed that too, the Spartan3E starter board dosent follow the
XAPP recommendation
KJ
>i dont have the luxury of a
> software tool to help me simulate and analyse, but i just want a good
> estimate which can be supported by theoretic statements.
A spreadsheet can give a rough estimate as well...more later
Look up the specs on the caps for the parasitic L and R. Now you can
build a spreadsheet that calculates the complex impedance Z as a
function of frequency of each cap type (i.e. 10uF, 4.7uF, etc.).
Knowing that, you can now compute the impedance of your PDS as a
function of frequency as well. Then graph it and you'll see your
expected impedance profile. You'll also want to factor in your PCB
impedance as well, but start with the caps.
>
> I know that the previous calculations assumed that the current demand
> for the harmonics were 2A for the entire bandwidth, but how does the
> current relate to the harmonics of a signal transitions? if i got
> 50Mhz swiching frequency will the current drop with 20db/decade, just
> as the amplitude of the harmonics?
I'm not sure where you're getting the 20dB/decade assumption since the
drop would depend entirely on the characteristics of the functions
being generated. If you could build a really good pseudo random
generator set of outputs from the FPGA, then one would expect a
roughly flat frequency response across the entire frequency band.
Most real designs though are not terribly random and would have some
rolloff but trying to take advantage of that in designing the power
delivery for an unknown FPGA design might not be the best approach.
By the way, going about figuring out the number and values of caps to
use based on current demand and voltage ripple over a frequency range
as you're doing is exactly the right approach. Don't forget about the
PCB stackup though, closely spaced power/ground plane pairs supply the
low impedance path that you'll need to connect up the caps (which are
the source of charge for the load) with the load itself. This PCB
impedance can be factored into that same spreadsheet model.
Kevin Jennings
Uwe Bonnes
> On Tue, 22 Jan 2008 01:00:49 -0800 (PST), kislo
> <kis...@student.sdu.dk> wrote:
> >... decoupling network ...
> > .. i dont have the luxury of a software tool
> > to help me simulate and analyse
> The headers in your post suggest you are using Windows. That's good,
> because you can download LTSpice and use that.
> http://www.linear.com/designtools/software/switchercad.jsp
Using LTSpice with wine on linux many times :-)
Marc Battyani
> Hi Kim,
> I've not got much time so here's a few pointers:-
>
> IMO, Xilinx publish excessive requirements which covers their arse if
> anything should go wrong. Fair enough. However, you should know that it's
> fairly difficult to get this wrong, indeed, some folks (not me!) on this
> newsgroup apparently use very few bypass caps.
I don't know what you mean by very few but, for the 1.2V VCCINT, I used 12
caps in my last big FPGA board ;-)
For a Stratix II 180 1.2V decoupling, I have:
5 x 2.2湩 LLM21 (under the FPGA)
4 x 10湩 LLL31 (under the FPGA too)
2 x 100湩 1210 caps nearby
1 x 1500湩 Tantalum cap farther.
I'm pretty happy with that stuff. I have a glitch less than 30mV when the
FPGA current goes from 2A to 25A in a few 盜.
I also put small coax connectors to be able to monitor the power rails at
least for the prototypes:
http://www.hirose.co.jp/cataloge_hp/e32124820.pdf
> Free capacitor parameter stuff.:-
> http://www.murata.com/designlib/mcsil/index.html
I use that too.
> Above a few 10's of MHz, all same sized caps have the same impedance. (See
> murata thing above) Just use 0402 1uF for everything. One per pin is more
> than enough. Make sure your board has a ground plane, try to use two vias
> for each cap terminal.
>
> Here's some stuff on where to place your caps.
>
> http://www.sigcon.com/pubsIndex.htm#bypass%20capacitors
>
> Or, ignore that stuff, sooo 20th C. Better bypass here:-
> http://www.x2y.com/
IMHO the LLM21 are better ;-)
Marc
Symon
news:19OdnZDlTN_j_Qva...@giganews.com...
>>
>> Or, ignore that stuff, sooo 20th C. Better bypass here:-
>> http://www.x2y.com/
>
> IMHO the LLM21 are better ;-)
>
> Marc
>
>
25 amps? You madman!
Anyway, if you get a spare moment, I'd appreciate you opinion of:-
http://www.x2y.com/bypass/measure/comparative_decoupling.pdf
pg. 16. They talk about "X2Y vs. Reverse Aspect Ratio Capacitors".
I'm planning on going for X2Y on my next design, but I'd be interested in
your analysis...
Cheers, Syms.
Symon
news:e6nbp3pah684v23q8...@4ax.com...
Hi Allan,
I second that. I thought I'd mention that there's also a Yahoo group for
LTSpice users.
http://tech.groups.yahoo.com/group/LTspice/
HTH., Syms.
Hal Murray
>Look up the specs on the caps for the parasitic L and R. Now you can
>build a spreadsheet that calculates the complex impedance Z as a
>function of frequency of each cap type (i.e. 10uF, 4.7uF, etc.).
The L depends strongly on how you connect the cap to the power/ground
planes. How many vias are you using? Where are they placed? What is
the via diameter? Is there a trace from the cap pad to the via? ...
--
These are my opinions, not necessarily my employer's. I hate spam.
John Larkin
<kis...@student.sdu.dk> wrote:
What we'd do is make sure each voltage has a pretty hunky copper pour
that's separated from the ground plane by a thin dielectric layer.
Then bypass each pour to ground with maybe four to six 0.33 uF, 0603
ceramic caps.
That's it.
John
kislo
decoupling capacitors ... if i switch 2A with a risetime of 0.5ns how
can i determine the current vs frequency or the impedance vs frequency
for the harmonics of 50Mhz switching frequency ... the impedance
requirement cant be constant over the complete frequency spectrum
Marc Battyani
>>> http://www.x2y.com/
>>
>> IMHO the LLM21 are better ;-)
>>
>> Marc
>>
>>
> Hi Marc,
>
> 25 amps? You madman!
I was surprised too and I had to redesign my power supply. :(
It's a Stratix II 180 full at 86% and running at 200MHz.
> Anyway, if you get a spare moment, I'd appreciate you opinion of:-
> http://www.x2y.com/bypass/measure/comparative_decoupling.pdf
> pg. 16. They talk about "X2Y vs. Reverse Aspect Ratio Capacitors".
> I'm planning on going for X2Y on my next design, but I'd be interested in
> your analysis...
They compared to an 8 pins IDC connector which has an ESL of 100pH. The
LLM21 has a 45pH ESL.
The 2 added pins make a big difference as they are placed on the short sides
of the caps.
Some people even prefer 0402s to X2Y:
http://www.freelists.org/archives/si-list/05-2005/msg00331.html
For decoupling the other supply rails, I used one 2.2µF 0402 per pin + 2 x
100µF 1210 and 1 x 1500µF Tantalum.
There are also other low ESL caps like the LGA and LICA:
http://www.avx.com/docs/catalogs/lga2t.pdf
http://www.avx.com/docs/catalogs/licarray.pdf
Marc
Symon
news:485539ea-77fc-4595...@m34g2000hsb.googlegroups.com...
Hi Kim,
There lies the problem. You're not going to get a proper answer without
considering the physical layout of the system. As Hal says, the layout and
attachment of the caps is as important as their own characteristics. Also,
remember that you're trying to bypass the IC die, not the pads for the BGA
on the PCB. So, the BGA package and its balls must be part of the
calculation, indeed it can have a significant effect. IC manufacturers embed
bypass caps in the package for good reason. All this must be taken into
account.
You should consider the design loaded into the FPGA. If you can reduce the
number of simultaneously switching circuits, the PDS requirement is easier
to meet.
The only way I know of to get an accurate answer to your question is to
model the whole lot in a 3-D field solver like HFSS. As you're a student (I
guess) maybe Ansoft will lend you a seat? You also need to talk to your FPGA
vendor to get models of their package. If you do this, we'd all be grateful
to see the results!
John's solution is a good one; I would maybe consider substituting the X2Y
parts for his 0603 parts. Try googling puddle site:x2y.com to read how a
copper 'puddle', like John's pours, can 'pool' vias.
Lastly, these days the capacitors are often cheaper than the cost to attach
them. Fewer more expensive parts can be a cost saver.
HTH., Syms.
Symon
>
>> Anyway, if you get a spare moment, I'd appreciate you opinion of:-
>> http://www.x2y.com/bypass/measure/comparative_decoupling.pdf
>> pg. 16. They talk about "X2Y vs. Reverse Aspect Ratio Capacitors".
>> I'm planning on going for X2Y on my next design, but I'd be interested in
>> your analysis...
>
> They compared to an 8 pins IDC connector which has an ESL of 100pH. The
> LLM21 has a 45pH ESL.
> The 2 added pins make a big difference as they are placed on the short
> sides of the caps.
>
> Some people even prefer 0402s to X2Y:
> http://www.freelists.org/archives/si-list/05-2005/msg00331.html
>
> 100湩 1210 and 1 x 1500湩 Tantalum.
>
> There are also other low ESL caps like the LGA and LICA:
> http://www.avx.com/docs/catalogs/lga2t.pdf
> http://www.avx.com/docs/catalogs/licarray.pdf
>
> Marc
>
>
Many thanks, that's very interesting. I misread the Murata datasheet and got
the LLMs mixed up with LLLs. (I must stop posting late after returning from
the pub!)
The AVX parts are neat too. That gives me plenty to think about.
Much appreciated, Syms.
Symon
>
> Some people even prefer 0402s to X2Y:
> http://www.freelists.org/archives/si-list/05-2005/msg00331.html
>
Syms.
John Larkin
<kis...@student.sdu.dk> wrote:
>well, im looking for a more theoretic answer for determing the
>decoupling capacitors ...
Why?
John
glen herrmannsfeldt
The Fourier transform of the (current) waveform will give you the
current vs. frequency spectrum. The actual problem comes with
the capacitor itself which, including its leads, will turn inductive
as the frequency increases.
-- glen
kislo
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Wed, 23 Jan 2008 00:28:27 -0800 (PST), kislo
>
> >well, im looking for a more theoretic answer for determing the
> >decoupling capacitors ...
>
> Why?
>
> John
hehe well, since i have to document my work, it would be nice to have
a proper analysis of the decoupling problem and not just use rules of
thumps all the way .. alot of decoupling problems are easy solved with
rules of thumps, but i think it would be nice to have a deeper
understandin of the problem, which perhaps will lead to better results
for my fpga board (and grades :o) .. but i see now that a deeper
analysis of decoupling a fpga, from a theoritic approach, is very
complex and will take to much of my time, which is already very
limited for this project .. but thank you all for the answers ;)
John Larkin
A worthwhile analysis would begin with knowing the current waveforms
that the fpga pulls on its various supplies. That would then be dumped
into the measured or estimated impedance of the bypassed power pours.
Does such current waveform info exist for your part, in your
application? If not, it's back to thumps.
I wonder if anyone here has encountered a situation where an fpga
failed because of inadequate bypassing. I've done dozens of Actel,
Lattice, and Xilinx apps, including mixed-signal stuff and
picosecond-jitter things, and I've never had a problem, even as I keep
ratcheting down on bypassing. So I don't understand why so much is
made over this issue.
John
Hal Murray
>A worthwhile analysis would begin with knowing the current waveforms
>that the fpga pulls on its various supplies. That would then be dumped
>into the measured or estimated impedance of the bypassed power pours.
>Does such current waveform info exist for your part, in your
>application? If not, it's back to thumps.
Has anybody tried writing nasty test code?
My straw man would toggle a lot of FFs for X cycles, then
do nothing for X cycles. Loop. Scan through various X
to see what happens.
Many years ago, there was a whole branch of hardware geeks
that did nothing but write memory tests. I wonder if that
sort of technology would be useful for FPGAs.
Falk Brunner
>> A worthwhile analysis would begin with knowing the current waveforms
>> that the fpga pulls on its various supplies. That would then be dumped
>> into the measured or estimated impedance of the bypassed power pours.
>> Does such current waveform info exist for your part, in your
>> application? If not, it's back to thumps.
>
> Has anybody tried writing nasty test code?
>
> My straw man would toggle a lot of FFs for X cycles, then
> do nothing for X cycles. Loop. Scan through various X
> to see what happens.
I did quite some time ago.
http://www.geocities.com/jacquesmartini
Try again some time later, ist just a cheap (free) account with 4MB/hour
and I just blew it :-0
Regards
Falk
Falk Brunner
>> A worthwhile analysis would begin with knowing the current waveforms
>> that the fpga pulls on its various supplies. That would then be dumped
>> into the measured or estimated impedance of the bypassed power pours.
>> Does such current waveform info exist for your part, in your
>> application? If not, it's back to thumps.
>
> Has anybody tried writing nasty test code?
OK, its available again.
http://www.geocities.com/jacquesmartini/digital/pldpower/pld_power_measurement.html
Regards
Falk
KJ
"Hal Murray" <hal-u...@ip-64-139-1-69.sjc.megapath.net> wrote in message
news:SMidnXjLmYc4uQHa...@megapath.net...
>
>>A worthwhile analysis would begin with knowing the current waveforms
>>that the fpga pulls on its various supplies. That would then be dumped
>>into the measured or estimated impedance of the bypassed power pours.
>>Does such current waveform info exist for your part, in your
>>application? If not, it's back to thumps.
>
> Has anybody tried writing nasty test code?
>
> My straw man would toggle a lot of FFs for X cycles, then
> do nothing for X cycles. Loop. Scan through various X
Not sure why doing nothing for X cycles is of any use.
It's fairly simple (and useful) to write code for something that simply
toggles every output pin on every clock and put each of those outputs at the
end of a long shift register so that internal flops in the device get used
as well. Run it at different clock speeds, if it's suits your needs. Been
there, done that....it's a good stress test.
KJ
Falk Brunner
>> My straw man would toggle a lot of FFs for X cycles, then
>> do nothing for X cycles. Loop. Scan through various X
>
> Not sure why doing nothing for X cycles is of any use.
To measure the broadband step response of your power supply network.
http://www.geocities.com/jacquesmartini/digital/pldpower/pld_power_measurement.html
> as well. Run it at different clock speeds, if it's suits your needs. Been
> there, done that....it's a good stress test.
It ist NOT enough!
Regards
Falk
Hal Murray
>> Has anybody tried writing nasty test code?
>>
>> My straw man would toggle a lot of FFs for X cycles, then
>> do nothing for X cycles. Loop. Scan through various X
>
>Not sure why doing nothing for X cycles is of any use.
I was trying to draw current at a lower frequency.
Adjusting X changes the frequency of the load.
Toggling everything would take the most current, but it
the on chip caps work well the rest of the system will see
a nice simple DC load. Waiting half the time will only
draw half as much current but at a lower frequency that
the power supply might not like.
KJ
"Falk Brunner" <Falk.B...@gmx.de> wrote in message
news:60410aF...@mid.individual.net...
> KJ schrieb:
>
>>> My straw man would toggle a lot of FFs for X cycles, then
>>> do nothing for X cycles. Loop. Scan through various X
>>
>> Not sure why doing nothing for X cycles is of any use.
>
> To measure the broadband step response of your power supply network.
>
> http://www.geocities.com/jacquesmartini/digital/pldpower/pld_power_measurement.html
>
>> as well.
Broadband step response is not terribly useful, you want to know what the
impedance is across the entire frequency band that the part can draw power
from. Sweeping the clock frequency with a design that toggles everything
and measuring supply voltage dips and looking for functional upsets is more
strenuous.
>> Run it at different clock speeds, if it's suits your needs. Been there,
>> done that....it's a good stress test.
>
> It ist NOT enough!
>
It's much more than a step response.
KJ
KJ
>
>>> Has anybody tried writing nasty test code?
>>>
>>> My straw man would toggle a lot of FFs for X cycles, then
>>> do nothing for X cycles. Loop. Scan through various X
>>
>>Not sure why doing nothing for X cycles is of any use.
>
> I was trying to draw current at a lower frequency.
> Adjusting X changes the frequency of the load.
>
frequency from DC to light will gather the information.
> Toggling everything would take the most current, but it
> the on chip caps work well the rest of the system will see
> a nice simple DC load.
I doubt that it would be a DC load. Those on chip caps get their charge
from the caps on the PCB through the PCB impedance. Those caps in turn get
their charge from other caps and PCB impedance and on back to the regulator.
None of that will make the chip look like a DC load. In fact if it did look
like a DC load then one wouldn't need to supply any capacitors on the board
since the regulator can certainly supply the current demands of a DC load.
> Waiting half the time will only
> draw half as much current but at a lower frequency that
> the power supply might not like.
>
No, the amount of current is only 'half' in some overall global measurement
of power draw. The chip needs to be supplied with the instantaneous current
that it demands to operate (otherwise it will fail functionally). The
instantaneous power demand of the part when it does make it's demand after
waiting is the same as if you hadn't waited at all. If it suddenly needs an
extra 1A on 'this' clock cycle, it won't matter that the last time it needed
the 1A was the previous clock cycle or if it was 'X' clock cycles ago...that
is until you get up to the point where the part is on the verge of failing
because the power distribution network of the entire system can not supply
the dynamic power quickly enough (which is what you're testing to try to
find).
KJ
Falk Brunner
> Broadband step response is not terribly useful, you want to know what the
> impedance is across the entire frequency band that the part can draw power
> from.
I think so. You can do a fourier transformation to convert the step
resonse into the freqeuncy domain.
> Sweeping the clock frequency with a design that toggles everything
> and measuring supply voltage dips and looking for functional upsets is more
> strenuous.
Iam afraid you are mixing this up with a frequency sweep using a SINE
wave signal, as you would do whn you measure a filter or something. But
a clock with variable frequency is NOT a sine wave. So the behaviour is
different. If you do continous toggling at different freqeuncies, your
voltage regulator will not be challenged, since it has only to supply a
constant current. Similar for low frequency caps. Only a burst signal
will stress ALL components. Read the link and think about it.
> It's much more than a step response.
OK, my fault. I mean a step resonse to a burst signal.
Regards
Falk
KJ
> KJ schrieb:
>
>> Broadband step response is not terribly useful, you want to know what the
>> impedance is across the entire frequency band that the part can draw
>> power from.
>
> I think so. You can do a fourier transformation to convert the step
> resonse into the freqeuncy domain.
>
What you're interested in is knowing what the effective source impedance of
the power supply network is across the entire frequency band of interest (DC
to light). Step response doesn't really do that very well.
>> Sweeping the clock frequency with a design that toggles everything and
>> measuring supply voltage dips and looking for functional upsets is more
>> strenuous.
>
> Iam afraid you are mixing this up with a frequency sweep using a SINE wave
> signal, as you would do whn you measure a filter or something. But a clock
> with variable frequency is NOT a sine wave.
Not at all. Those toggling flip flops are all squarish waves and each of
them toggling presents a whole slew of harmonics to the entire power supply
system.
> So the behaviour is different. If you do continous toggling at different
> freqeuncies, your voltage regulator will not be challenged, since it has
> only to supply a constant current.
Nope, not DC....but your PCB/caps do need to be designed adequately so that
the regulator is only being called on to supply current over a relatively
small frequency range since the output inductance that it presents will
prevent it from supplying any high frequency current. Maybe you're missing
that when I say to sweep the clock frequency I'm not meaning just somewhere
around the operating point but all the way from DC up to as high as you can
go with the part.
> Similar for low frequency caps. Only a burst signal will stress ALL
> components. Read the link and think about it.
>
Again, every toggling output is a squarish wave and the chip will be making
demands for current over a broad frequency range, regardless.
Kj
John Larkin
A gated clock would be a severe bypassing test, since the "DC" current
draw would jump as the clock started and stopped, which would stress
the low-frequency transient response of the caps and the regulators.
This could easily be a bigger hazard than the GHz stuff.
We've recently done some gated clock things, with switching supplies,
without problems. A lot of bulk low-esr capacitance is a good idea
here, if your regulator stays stable.
John
John Larkin
wrote:
>
>"Hal Murray" <hal-u...@ip-64-139-1-69.sjc.megapath.net> wrote in message
>news:X-idnQg32c4zUwHa...@megapath.net...
>>
>>>> Has anybody tried writing nasty test code?
>>>>
>>>> My straw man would toggle a lot of FFs for X cycles, then
>>>> do nothing for X cycles. Loop. Scan through various X
>>>
>>>Not sure why doing nothing for X cycles is of any use.
>>
>> I was trying to draw current at a lower frequency.
>> Adjusting X changes the frequency of the load.
>>
>OK, but so does simply changing the clock frequency. Sweeping the clock
>frequency from DC to light will gather the information.
Burst clocking will generate, potentially, amps of low-frequency
transient loading on the power supply. Slowing down a constant clock
will not have that effect, since the average Vcc current will fall as
the clock frequency falls.
This current waveform...
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is a heap different from this one:
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John