5 V oscillator output to GCLK
maverick
I am using a Spartan3 xc3s1000-4 fg456 FPGA. I have an oscillator
which gives clk output at 5V p-p swing. I am using the FPGA in LVTTL
mode which works on 3.3 V signaling. Is it OK to feed the 5V clock to
one of the GCLK pins of the Spartan 3 FPGA? Should I put a current
limiting resistor in the clock path before I feed it to the GCLK pin?
Any issues with that?
Best Wishes,
Farhan
Brian Drummond
Better to use a resistive divider to (a) drop the 5V to 3.3V and (b)
match the impedance of the signal trace. My preference would be for
series termination, i.e. place the resistive divider at the oscillator
end, assuming the clk trace is a simple trace (no major stubs feeding
different destinations).
If the oscillator can't drive such a low impedance, you need a higher
impedance divider. Then I would place it aas close as possible to the
Spartan pin.
- Brian
Kolja Sulimma
> My preference would be for
> series termination, i.e. place the resistive divider at the oscillator
> end, assuming the clk trace is a simple trace
Do both:
One resistor in series at the source, one resistor to ground at the
destination.
You get a transmission line that is terminated at both ends. A
reflection caused
by a mismatch at the destination is dampened at the source.
This provides essentially the best signal quality you can get. The
only disadvantage
is the reduced swing at the destination. But this is exactly what the
OP wants.
Kolja Sulimma
David Spencer
"Kolja Sulimma" <ksul...@googlemail.com> wrote in message
news:0d885ecd-0839-416b...@34g2000hsh.googlegroups.com...
A better solution would be to feed the clock through a 3.3V buffer that is
5V tolerant. An AHC family device would do the job I think. In fact, a
74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin
package.
KJ
>
> A better solution would be to feed the clock through a 3.3V buffer that is
> 5V tolerant. An AHC family device would do the job I think. In fact, a
> 74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin
> package.- Hide quoted text -
>
By what measure would an IC be a "better solution" than two resistors?
KJ
John_H
I just got a 3.3V oscillator driving a 2.5V input working. The
oscillator has miserable drive capability and I suspect the 5V
oscillator you're using may have poor drive capability as well.
Unless you have a rare high-drive oscillator OR if you're oscillating
at a leisurely rate, do like the FPGA vendor recommends: use a 100 ohm
series resistor.
If you use a resistor divider, your parasitics can severely slow down
your edges. Our 125 MHz oscillator looked almost like a sine wave and
was reduced in amplitude to the point we were getting 25% duty cycle.
Not good for our application. If it was a 20 MHz oscillator, the
resitor divider would probably be fine. If we could deal with 25%
duty cycle we could have probably used what was there. The series
resistor just plain works. The input protection on the Spartan3 is
pretty robust so you can drive the many milliamps (if you have many
milliamps) into the protection diode without affecting reliability.
If I wanted to be detailed, I'd understand the drive capability, the
frequency, and the parasitics involved.
- John_H
Jim Granville
Or, think like a scope probe, and do a capacitive divider, That
preserves the edges, and allows higher value resistors (so saves power)
Measure the pin/pcb capacitance, and Osc output swing, and then
calculate the driving capacitance, likely to be in tne 30-40pF region.
Or, add a LVC1G57/58/97/98 to your parts list, and use that.
-jg
David Spencer
news:cf46e434-c521-4155...@27g2000hsf.googlegroups.com...
> KJ
Static drive current.
Assuming the divider is matched to the impedance of the trace, as originally
suggested, the oscillator would need to source and sink around 100 mA.
Peter Alfke
> "KJ" <kkjenni...@sbcglobal.net> wrote in message
Make that 50 mA, if the series resistor is 50 Ohm, and the parallel
destination termination another 50 Ohm.
Peter Alfke
Jon Elson
You don't want slow clock transitions, and high drive impedances at
the receiving end. Now, the right choice of resistors probably won't
cause such trouble, but it at least needs to be considered. A long
clock trace (bad idea, anyway) fed with a series resistor is essentially
a lumped-constant low-pass filter. I'm not sure how fast Spartan III
is, but if the Tr got slowed to tens of nS it would be really dangerous.
Just add a little on-chip or on-board noise, and you have extra clock
transitions. I've seen this on a 5V Spartan setup that got its clock
from an LVDS receiver. Some reflections on the LVDS cable caused
multiple clocks that the Spartan FFs responded to. I'm sure this would
only be more sensitive on Spartan 3.
I just did a board that had a bunch of logic turned upside down (-5 V
and ground) and used resistive networks with matching caps across the
series resistor to keep the edges sharp. This had to be done some
70 places on the board, and there's no suitable chip for such a
conversion. It worked, but had me sweating until proven.
Jon
KJ
"David Spencer" <davidm...@verizon.net> wrote in message
news:WO2Vj.1895$Uz2.1141@trnddc06...
Oscillator outputs typically can't drive PCB trace impedance types of values
(i.e. 50-100 ohm) anyway so you wouldn't terminate it with that low of a
resistor value. Instead you would use something quite a bit higher so that
you would get the edge quality that you need and the divider to limit the
input voltage to the part.
The 5<-> 3.3V ICs are nice when you have a bunch of signals that need
translating (like a bus) but if it's just a single net (or a small handful)
the resistors work nicely....of course it begs the question of why not use a
3.3V oscillator in the first place.
KJ
KJ
"maverick" <sheikh....@gmail.com> wrote in message
news:867bdf28-6f10-4dd4...@m44g2000hsc.googlegroups.com...
Any reason why you wouldn't just use an oscillator that has a 3.3V swing to
begin with?
KJ
KJ
"Jon Elson" <el...@wustl.edu> wrote in message
news:4824C322...@wustl.edu...
>
>
> KJ wrote:
>> On May 9, 11:53 am, "David Spencer" <davidmspen...@verizon.net> wrote:
>>
>>
>>>A better solution would be to feed the clock through a 3.3V buffer that
>>>is
>>>5V tolerant. An AHC family device would do the job I think. In fact, a
>>>74AHC1G04 would be perfect - it's a single inverter in a tiny five-pin
>>>package.- Hide quoted text -
>>>
>>
>>
>> By what measure would an IC be a "better solution" than two resistors?
> You don't want slow clock transitions, and high drive impedances at
> the receiving end. Now, the right choice of resistors probably won't
> cause such trouble, but it at least needs to be considered.
I was answering within the context of what info the original poster provided
which was that he has a 5V signal going into a 3.3V tolerant input. No
mention of any other similar signals that might also be problems, or that
the clock is a long distance away or anything, just looking for a way to use
(for some unknown reason) a 5V osc into a 3.3V tolerant part.
> A long clock trace (bad idea, anyway) fed with a series resistor is
> essentially a lumped-constant low-pass filter. I'm not sure how fast
> Spartan III is, but if the Tr got slowed to tens of nS it would be really
> dangerous.
The same can happen with any driver. An electrically long net will need to
be terminated
KJ
Peter Alfke
receiver, each with a resistor that equals the characteristic
impedance of the clock trace, then a fast transition sees just a
resistive divider, not a lumped capacitance.
That's the beauty of terminated transmission lines...
Peter Alfke
Jim Granville
>
> When you series-terminate the driver, and parallel-terminate the
> receiver, each with a resistor that equals the characteristic
> impedance of the clock trace, then a fast transition sees just a
> resistive divider, not a lumped capacitance.
> That's the beauty of terminated transmission lines...
That's true, until it bangs into the lumped input capacitance of the
FPGA.
You also get a voltage-loss with this focus on transmission
line matching, which might give noise margin issues, as
well as Buffer Current adders, from the lower Vih.
-jg
Peter Alfke
wrote:
Let's not forget: "Voltage loss" was the purpose of the whole
exercise...
Peter
Jim Granville
I should have been clearer :
Equal Source/Load terminations will turn the 5V swing into 2.5V Hi, on a
3.3V system.
The ideal Vih is 3.3V, (lowest power, best noise immunity), so this
is a lower Vih, which was the 'voltage loss' I was getting at.
-jg
Peter Alfke
So let's reduce the series resistor at the source to 25 Ohm, and keep
the parallel termination at the destination at 50 Ohm.
That puts 2/3 of Vcc on the cable and the FPGA input = 3.3 V. The 25
Ohm includes the drive impedance, which might mean no external series
resistor at all...
Peter
pdud...@comcast.net
Or even better, for a little more money you could use an oscillator with
differential LVDS or LVPECL output. Differential signalling would reduce
jitter and EMI.
Jim Granville
Yes, that would work, However....
# You are no longer doing strict series-impedance-match termination
# One can tell you are used to high-power FPGAs ;)
- as this sugestion adds a cost of 33mA in power budget (@50% clk duty
cycle).
Suppose the target was a Zero power CPLD ?
The whole device Icc might be 14.6mA at 200Mhz - 7.5mA @ 100MHz.
[OP did not mention speed, but 5V sources are << 100Mhz ]
The clock-terminator is consuming far more power than the CPLD !
-jg
KJ
"Jim Granville" <no....@designtools.maps.co.nz> wrote in message
news:4825...@clear.net.nz...
> Peter Alfke wrote:
>
>> So let's reduce the series resistor at the source to 25 Ohm, and keep
>> the parallel termination at the destination at 50 Ohm.
>> That puts 2/3 of Vcc on the cable and the FPGA input = 3.3 V. The 25
>> Ohm includes the drive impedance, which might mean no external series
>> resistor at all...
>> Peter
>
> Yes, that would work, However....
>
> # You are no longer doing strict series-impedance-match termination
> # One can tell you are used to high-power FPGAs ;)
Oscillators typically can't drive 50 ohms impedances either so impedance
matching to the PCB would not be relevant....the optimal solution would be a
series resistor of ~1.75x - 2x, parallel to ground of 3x where 'x' needs to
be determined based on the spec'ed drive capability of the oscillator. An
IBIS or Spice model would determine 'x'. Assuming the osc to be 50MHz or
less, a PCB impedance of ~50 ohms, I'd suspect that x ~ 50-75 would give
good signal quality and meet Vih requirements at the FPGA.
> - as this sugestion adds a cost of 33mA in power budget (@50% clk duty
> cycle).
>
> Suppose the target was a Zero power CPLD ?
> The whole device Icc might be 14.6mA at 200Mhz - 7.5mA @ 100MHz.
> [OP did not mention speed, but 5V sources are << 100Mhz ]
>
> The clock-terminator is consuming far more power than the CPLD !
>
If power consumption was even remotely close to the case that the OP was has
in mind he wouldn't bother with any of this...he would've replaced the 5V
osc with a 3.3V one. Presumably there is some reason for even wanting to
have a 5V osc on the board in the first place, but minimizing power
consumption is not the reason.
Kevin Jennings
KJ
KJ
Peter Alfke
Just to belabor a point: When the output side of a transmission line
is parallel-terminated, there is no requirement to also properly
terminate the driving side. Using a "wrong" series resistor to adjust
the amplitude is ok, since there is no signal coming back to the
driver, and thus no need for proper termination at that end.
Peter Alfke
Kolja Sulimma
> A long clock trace (bad idea, anyway) fed with a series resistor is essentially
> a lumped-constant low-pass filter.
No. It is a transmission line with an impedance matched driver. You
can get any
frequency accross that setup that you like.
> I'm not sure how fast Spartan III
> is, but if the Tr got slowed to tens of nS it would be really dangerous.
The setup will not change the rise time of the signal. The slew rate
will be halved,
because the voltage swing is halved, but that's it.
The receiver will see the same waveform as the source with halve the
voltage.
But other posters where correct with noting that the oscillator needs
to be capable
to drive a 100R transmission line, which might not be the case.
Kolja Sulimma
glen herrmannsfeldt
> On 9 Mai, 23:33, Jon Elson <el...@wustl.edu> wrote:
>> A long clock trace (bad idea, anyway) fed with a series
>> resistor is essentially a lumped-constant low-pass filter.
> No. It is a transmission line with an impedance matched driver.
> You can get any frequency accross that setup that you like.
If matched with the characteristic impedance it works
like a transmission line, if not it looks like a capacitor
or inductor depending on the termination.
The phone system (US, anyway) seems to use 600 ohm termination
on about 100 ohm UTP cable. The result is that the cable looks
like a capacitor and, for long lines, results in a high frequency
drop off.
http://en.wikipedia.org/wiki/Loading_coil
The telephone solution is loading coils that increase the
series inductance (on average) resulting in a flatter
response to the required 4kHz, and a sharp drop after that.
The effect also shows up in antenna design when the frequency
doesn't match the appropriate length for the antenna elements.
As previously stated, though, it is only necessary to match
one end. If the sink impedance is matched the voltage will
be reduced appropriately by the series source resistor
and the cable impedance as a voltage divider.
-- glen