DCM Autoconfiguration??

[motty]

I have ported a project that was developed on an ML401 Virtex4 board
over to an Avnet Virtex4 PCI-E board. The ML401 uses a V4LX25 and the
Avnet board uses a V4FX60. The only changes I made to the project had
to do with just reassigning signals in the UCF.

I have 2 DCM's in the project. Each DCM's lock signal is routed out
to an LED on the board. Each DCM's output clock is routed to a header
pin (as well as elsewhere in the design). After configuration (or
after a pushbutton RESET to the FPGA) the lock LED's light and the
output clocks are valid. This lasts about half a second. Then
everything goes dead. So lock is high and valid clocks are output for
at least hundreds of thousands of cycles. Then nothing. I can press
the RESET button (resets the DCM's -- their lock's are used to
distribute sync resets to the rest of the logic in the design) and the
lock LED's light and the clocks are valid -- again, only for about
half a second.

One difference I noticed is that the ISE reports that the DCM
hierarchical names have changed due to DCM Autocalibration. There are
also multiple refences to this DCM autocalibration in various
reports. I have never heard of this, and I can't find info on Xilinx
site. Is there something different that happens with DCM's on V4FX
parts compared to V4LX parts? I have checked Avnet app notes on this
board. Their UCF doesn't have anything special in it that I
overlooked.

This is a weird problem I haven't looked in to very hard. Thought I
would ask here to see if it is a bonehead move on my part : )

Thanks!

[motty]

Sorry, it is late. The subject should be DCM AutoCALIBRATION not
Autoconfiguration.

[motty]

I should try searching for the correct term. I've found the info on
Xilinx' site. I still don't know why the thing is failing though....

[Erik Widding]

On Mar 15, 10:49 pm, "motty" <mottobla...@yahoo.com> wrote:
> I have 2 DCM's in the project. Each DCM's lock signal is routed out
> to an LED on the board. Each DCM's output clock is routed to a header
> pin (as well as elsewhere in the design). After configuration (or
> after a pushbutton RESET to the FPGA) the lock LED's light and the
> output clocks are valid. This lasts about half a second. Then
> everything goes dead. So lock is high and valid clocks are output for
> at least hundreds of thousands of cycles. Then nothing.

> [...]

> One difference I noticed is that the ISE reports that the DCM
> hierarchical names have changed due to DCM Autocalibration. There are
> also multiple refences to this DCM autocalibration in various
> reports.

I just went through this last week. Had the same behavior. Went
about the debug the same way that you did. Turning off the DCM
autocalbration soved the problem. THe following line in your UCF will
work:
INST dcm_0/dcm_0/Using_DCM_ADV.DCM_ADV_INST
DCM_AUTOCALIBRATION="FALSE";
(Substitute the name of your DCM for mine...)

Regards,
Erik.

---
Erik Widding
President
Birger Engineering, Inc.

(mail) 38 Chauncy St #1101; Boston, MA 02111
(voice) 617.695.9233
(fax) 617.695.9234
(web) http://www.birger.com

[motty]

Yep, that is what I did. I have my DCM configured such that the CLKFB
is not connected. I don't really need it for my application and
thought I would save some clock buffers. Apparently, the DCM Autocal
circuitry will hold the DCM in reset if EITHER the CLKFB or CLKIN
loses a clock signal. Well, CLKFB never had one, so I guess the
Autocal cicuitry waits for lock until it performs its function.

So now I have everything working as should be!

Thanks for the reply!