FPGA Gate Counts: No Truth in Advertising
da...@lowrance.com
A while back one of my co-workers brought me an article he'd clipped
out of a magazine. Actel had a new part that would hold 20K gates
with 100% utilization... or so they claimed. At the time we were just
getting started on a small ASIC, about 14K gates. "Great", I said.
"We'll be able to create a prototype and use that one FPGA to test our
entire design." It was not to be. The problem was that the 20K gate
part would barely hold 10K 'real' gates.
This wasn't my first run-in with an FPGA company whose parts turned
out to be smaller in real life than advertised. Last year an ASIC
which we wanted to prototype in a Xilinx 4000 series part turned out
the same way. The FPGA industry has come a long way by learning from
the ASIC industry. Design methodologies are constantly improving and
support for HDLs gaining momentum. Can someone tell me why the FPGA
industry is having such a hard time learning to count?
David Gardner
--
David N. Gardner
ASIC Design Engineer Lowrance Electronics
da...@lowrance.com 12000 E. Skelly Drive.
918 437-6881 x8583 Tulsa OK, 74128
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Brad Taylor
da...@lowrance.com wrote:
>
> A while back one of my co-workers brought me an article he'd clipped
> out of a magazine. Actel had a new part that would hold 20K gates
> with 100% utilization... or so they claimed. At the time we were just
> getting started on a small ASIC, about 14K gates. "Great", I said.
> "We'll be able to create a prototype and use that one FPGA to test our
> entire design." It was not to be. The problem was that the 20K gate
> part would barely hold 10K 'real' gates.
>
> This wasn't my first run-in with an FPGA company whose parts turned
> out to be smaller in real life than advertised. Last year an ASIC
> which we wanted to prototype in a Xilinx 4000 series part turned out
> the same way. The FPGA industry has come a long way by learning from
> the ASIC industry. Design methodologies are constantly improving and
> support for HDLs gaining momentum. Can someone tell me why the FPGA
> industry is having such a hard time learning to count?
The short answer is greed.
The longer answer is that there really is no good way to relate FPGA
features to ASIC nand gates. When the answer is undefined, the
marketing guys will always promote the most optimistic estimate. It
probably got started like this.
Marketing: How big is that new FPGA thing?
Engineering: Well, it has 400 4LUTS:DFFs and registers in the IO blocks.
Marketing: No, I mean how big is it?
Engineering: Well we have two design which just fit. One is from a 6K
ASIC and the other is from a 4K ASIC.
Marketing: (Lets see 6+4 = 10) OK, gotta go.
But seriously folks:
Can someone tell me what is a real gate?
FPGA feature metrics
-gates/DFF?
-gates/4LUT?
-gates/4SRAM?
-gates/carry_generator?
-gates/tristate_bus_line?
-gates/interconnect_switch?
Software metrics
-gates/16 bit operator?
-gates/line_of_code?
System metrics
-gates/unrouted_fpga
-gates/routed_fpga
-gates/fpga_at_10MHz
-gates/fpga_at_50MHz
-ASIC_gate/FPGA_gate
Financial metrics
- VHDL_gates/hr
- Schematic_gates/hr
- Debugged_gates/hr
- delivered_to_a_customer_and_used_gates/hr
- Gates/mm_silicon
- Gates/pin
- Gates/$
Just messing around while I wait for a 10K_gate_FPGA to route:
routing metric = 10K_gates/29min * 50%full= 10K gates/hr.
design metric = 2 days = 5k/16hrs = 300 gates/hr
debug metric = I wish I knew!
-
Brad
da...@lowrance.com
In article <3293BB...@emf.net>,
Your right. This can be a confusing problem and anybody who wants to
could come up with new ways of measuring their parts, new metrics that
give whatever appearance they wish. I do however think it is possible
to take a logical approach to this issue.
Paul Hardy, a Xilinx FAE, emailed me with his thoughts on the subject.
He included a link to a Xilinx app note which discusses how Xilinx
counts gates ( http://www.xilinx.com/xapp/xapp059.pdf ).
The first approach Xilinx took to calculating the Maximum Logic Gates
was to analyse the fundamental building block of their architecture,
the CLB, and determine how it relates to the logic gates of a typical
ASIC vendor. Here's what they came up with for a 4000 series part:
CLB Resource Gates
-----------------------------------
4-input LUT (2 per CLB) 1 to 9
3-input LUT 1 to 6
flip-flop (2 per CLB) 7 to 12
TOTAL 17 to 48
We can also look at other vendors this way too. For example, the
Actel 3200 family. These parts are based on a finer grained
architecture than the Xilinx 4000 series. The fundamental block
of the 3200 series part is a Logic Module:
LM Resource Gates
-----------------------------------
AND 2
OR 2
4 input mux 7
flip flop (in half of LMs) 7 to 12
TOTAL 14.5 to 17
These numbers give us an idea of what is possible (with the perfect
design). The obvious problem though is that there is no such thing as a
perfect design. In the real world we'll never have a design that
uses every element of every FPGA logic block. These numbers can still
be very useful however for comparing different FPGA structures.
But the original question still stands. If I have a design that takes
X number of ASIC NAND gates then how do I know what FPGAs it will fit
into. I think the only way to determine this is through empirical
data. If we were to take a variety of designs of known size (in terms
of ASIC NAND gates) and route them into an FPGA then we could determine
a real-life number representing the average number of gates per logic
module. This would truely be useful. And by the way Xilinx claims to
have done this. According to that app note I mentioned previously
Xilinx claims they can get an average of 26 gates per CLB. In my
experience the actual number is _much_ lower, on the order of 10. And
yes this means that my design which utilized a 4010 maxed out at about
4K gates... significantly lower than Xilnix's minimum number of 7K.
I should note that buried in the Actel documentation is a table that
gives "Average Gates Per Module". According to this table a 3200 series
part will hold about 4.8 gates per module. This is very close to what
I've seen which was about 4.5. But for the 3200 series part they claim
holds 20K gates if you calculate its size using the 4.8 number from
their own documentation you only get about 12K.
I want to encourage everyone to post a reply to this message, including
vender FAEs or reps. I want to hear about the experiances of others and
to know what kinds of utilization other designers have seen with Xilinx,
Actel, or any other FPGA.
David Gardner
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Tom Standley
da...@lowrance.com wrote:
>A while back one of my co-workers brought me an article he'd clipped
>out of a magazine. Actel had a new part that would hold 20K gates
>with 100% utilization... or so they claimed. At the time we were just
>getting started on a small ASIC, about 14K gates. "Great", I said.
>"We'll be able to create a prototype and use that one FPGA to test our
>entire design." It was not to be. The problem was that the 20K gate
>part would barely hold 10K 'real' gates.
>
>
Couldn't something like the PREP benchmarks (http://www.prep.org) be
used to compare FPGA's? I'm just starting to look into this but it
appears that they have several standard designs with synthesis results
for several parts from a number of vendors.
Wouldn't a comparison of the synthesis results of several parts using
the same tool set give an indication of the effective size of the part
for the type of design indicated by the benchmark?
Andy Gulliver
A simple, one word answer - 'Marketing'
Any relationship between FPGA vendors' claimed gate count and your real
experience is pure coincidence!
The only sure-fire way to evaluate whether or not your application will
fit into a particular device is to compile/fit the design....
--
Regards
AndyG
**************************************************
*Any opinions expressed herein are entirely mine,*
*unless expressly stated otherwise. *
*(as if anybody else would admit to them.....) *
**************************************************
Ron Wilson
da...@lowrance.com wrote:
>
> In article <3293BB...@emf.net>,
> Brad Taylor <b...@emf.net> wrote:
> >
> > The short answer is greed.
> > The longer answer is that there really is no good way to relate FPGA
> > features to ASIC nand gates. When the answer is undefined, the
> > marketing guys will always promote the most optimistic estimate. It
> > probably got started like this.
> > Marketing: How big is that new FPGA thing?
> > Engineering: Well, it has 400 4LUTS:DFFs and registers in the IO blocks.
> > Marketing: No, I mean how big is it?
> > Engineering: Well we have two design which just fit. One is from a 6K
> > ASIC and the other is from a 4K ASIC.
> > Marketing: (Lets see 6+4 = 10) OK, gotta go.
At FPGA96 last spring, someone proposed that we use new nomenclature for the
vendor's claims on gate capacity. Analogous to the idea that dogs seem to get
more lifetime out of a year that we do--hence, a "dog year" being equivalent
to about seven person years--he suggested that vendors be required to specify
the capacity of their parts in "dog gates."
Anyway. There is certainly a big difference between what the nomenclature
says and what you can fit into a part, most of the time. There are in fact
very ordered, repetitive designs that will come close to the nominal capacity
on some FPGAs, but they are not common sorts of circuits.
The problem, as other posters have said, is that the marketing department
counts logic resources and adds them up, at so many "gates" per LUT, etc. If
an FPGA has relatively fine grain, so that you are using most of the
resources in each logic block, and it has a surplus of interconnect, so that
you can in fact use nearly every logic block without getting a 10 kHz design,
then this is a fair estimate of chip capacity.
But trends are going the other way. With sub-micron processes and three-layer
metal, the interconnect takes up all the chip area, and the logic just kind
of lies there underneath. So there is no penalty for a vendor to make the
logic block more complex than the average design can use. After all, the
silicon is just sitting there otherwise. This is a big help in implementing
some types of circuits, in fact, because is can reduce the number of blocks
you need and localize some operations to a single block.
But it makes the "count-'em-up" approach to capacity even less accurate. Now,
you are very unlikely to use most of the stuff that is in the logic blocks.
So the difference between dog gates and your gates gets even bigger, even
though the FPGA may be better for your application than the previous
generation would have been.
There have been attempts to solve this. Actel used to rate their parts based
on the number of gate-array gates necessary to implement a circuit that just
fit in the FPGA. They have unfortunately abandoned this nobel idea. PREP,
Stan Baker's organization, had an industry-wide benchmarking effort going for
a while. It produced very useful data that did in fact give you an accurate
picture of how a part would behave on a particular type of design. But,
predictably, as soon as the results trod on marketing toes, companies began
to withdraw from the group. Marketing departments came up with scalar
"figures of merit" based on the whole suite of PREP benchmarks, with math
that made the Minkovsky Metric look like arithmetic. And, to be fair, as FPGA
capacities increased, the original benchmark circuits, used step-and-repeat
fashion to fill the chips, became less useful.
Baker is, I believe, working on a new benchmark methodology based on
synthesis of real-world, large designs. If he is getting as much cooperation
from the industry as he did last time, he can use all the independent support
he can get. You might look him up. He posts here every once in a while, or is
reachable at sba...@best.com.
ron wilson, ee times
Ross Swanson
da...@lowrance.com wrote:
>
> A while back one of my co-workers brought me an article he'd clipped
> out of a magazine. Actel had a new part that would hold 20K gates
> with 100% utilization... or so they claimed.
we did a design that overran the utilization by 20%, we could keep
removing bits and pieces of test logic until we got the design to
fit and route with just one or two spare 'blocks', actel 14100.
It was my impression that 'gate' comparsion is made more difficult
by the granularity of the FPGA.
Peter Alfke
PREP was a good idea that went sour due to super-aggressive marketing.
To accomodate all programmable devices, even the lowliest CPLD, the test
circuits were made very small. ( e.g. loadable 16-bit counters ) and
were then replicated until the device was full. Each circuit had as many
inputs as outputs, so they could be concatenated like Lego blocks.
Obviously, each company wanted to be the best,so we all put in a lot of
effort to pack our devices and to achieve an impressive speed. Density
was not much of an issue, since the routing was trivial, only neighbors
talking to neighbors. ( How's that for meaningful benchmarks ?)
Then came the dirty tricks.
Altera managed to defeat the spirit of the exercise by exploiting an
oversight in two of the circuits,where common logic could be pulled out
and be implemented only once per device. This gave them great packing
density, a victory of synthesis over benchmarking.
In order to level the playing field, everybody else then had to do the
same stupid thing. "To hell with meanigful data, as long as everybody
can brag about some unrealistic achievement".
This left such a bad taste in my mouth that I resigned from the
committee.
Peter Alfke,speaking for himself.
John Vincent
It appears that discussion on this thread has died out, but I'll add my two
cents worth. The problem here is another classic case of mononumerousis,
that dreaded disease most common to marketing and management. Device
capacity is a complex quantity of several dimensions and cannot possibly
be expected to be adequately described by a single number. This has been
true since PLDs were first invented, when device architectures were fairly
simple and regular, before the myriad of special functions and architectural
enhancements. This has only added additional dimensions to an already very
complex problem. The best one can hope for when taking a simplistic approach
to determining device capacity is to derive some statistical measures and
to determine reasonable practical limits. And vendors are beginning to do
this. At least one is even openly describing the assumptions and equations
used to obtain the "nominal" device capacity ratings and ranges for
practical applications. This is definitely a step in the right direction.
It is important for the designer to realize what these numbers mean and
how to use them. One way is consider them in a somewaht analogous fashion
to component power ratings. A good designer will de-rate them in order to
achive better reliability. The principle hold here as well, but the derating
factor isa bit larger....
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******* ************* John Vincent
****** **************** Eastman Kodak Company
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