Jun 21, 2021, 9:49:16 AM6/21/21
Hi FPGA Experts,
How can we measure ps of delays in FPGA with minimum area and good accuracy ?
Today's TDC (Time to Digital Converter) architectures suffer lot of drawbacks
like high gate utilization, High number of delay cells required for high resolution, Longer dead time, dependant on PVT conditions etc.