Free SPARC VHDL model available

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jg...@ws.estec.esa.nl

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Oct 7, 1999, 3:00:00 AM10/7/99
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LEON-1 VHDL model

Background

The LEON core is a SPARC compatible integer unit developed at ESTEC. It
has been implemented as a highly configurable, synthesisable VHDL model.
To promote the SPARC standard and enable development of system-on-a-chip
(SOC) devices using SPARC cores, the full source code is made freely
available under the GNU GPL license.

Architecture

LEON-1 is a SPARC compatible processor targeted for embedded
applications. It features the following functions:

LEON SPARC compatible integer unit
separate instruction and data caches
32-bit memory bus with EDAC, PROM and SRAM support
interrupt controller,
two 24-bit timers
two UARTs
16-bit I/O port
write protection
power-down function
watchdog.

Synthesis

The VHDL model is fully synthesisable and contains synthesis scripts for
Synopsys-DC and Synplify. Targeting a 0.35 um CMOS process (gate-array
or std-cell), approximately 100 MHz can be reached with a gate count of
35 Kgates. The processor also fits in an Altera 10K200E FPGA, utilising
65% of the device and running at 15 MHz.

Simulation

The model comes with a generic testbench and test program, and includes
support files for the Modelsim simulator. It also features a built-in
disassembler for debug purposes.

Software tools

Currently, software for LEON can be developed by reusing the ERC32CCS
compiler for ERC32. However, no support exists for the LEON peripherals
(timers, UARTs) limiting the usability of the compiler. An adaptation of
ERC32CCS for LEON is in progress and will
be made available in Q1 2000.

Download

Documentation and VHDL source code can be obtained at:

http://www.estec.esa.nl/wsmwww/leon/


Jiri Gaisler
European Space Agency


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