has anyone made PLB_DDR work with 1Gb DRAM chips?

[Jeff Cunningham]

I have a design that consists in part, of the DDR interface from the
ML403 board, but with two of these 1Gb DDR parts:

http://www.micron.com/products/partdetail?part=MT46V64M16P-6T%20IT

instead of these 256Mb parts that were on the original ML403:

http://www.micron.com/products/partdetail?part=MT46V16M16TG-6T

This should increase the memory from 64MB to 256MB, as explained in the
ML403 User Guide. On the PLD_DDR instance in the mhs file, I increased
the row and column addresses each by 1, increased the memory space on
the PLB bus by 4x, and hooked up the additional address pin in the mhs
and ucf files. But memory operation is erratic - when writing several
words, often all words read back as the last value written to the last
word. Also, sometimes the middle bytes come back FF's. When I configure
the design for the smaller memory chips, the 1Gb chips suddenly start
working correctly, but of course the memory is the old 64MB size.

Has anybody made the PLB_DDR design work with 1Gb chips? I tried using
the MPMC, which worked - but it used an unacceptable amount of
resources. I opened a webcase, but they have been little help - I'm
hoping someone here has some experience/advice to share before I dive
into it deeper.

thanks in advance,
-Jeff