create a RAM in a Virtex
Gerhard Griessnig
My problem is that my RAM has a width of 200 bits.
Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?) without a complex addressing.
Futhermore i tryed to create a RAM with the XILINX Coregenerator but i got an error message
Error L-44/C0 : #0 Error: D:/programs/xilinx/active/projects/grieda02/ram.vhd
line -44 Library logical name XILINXCORELIB is not mapped to
a host directory. (VSS-1071) (FPGA-dm-hdlc-unknown)
Error L48/C0 : #0 Error: D:/programs/xilinx/active/projects/grieda02/ram.vhd
line 48 No selected element named C_MEM_SP_BLOCK_V1_0 is defined
for this prefix. (VSS-573)
2 error(s) 0 warning(s) found
Does anyone has an idea, or does anyone has a vhdlcode ?
THANKS Gerhard
K. Orthner
13 BlockRAMs. (well, 12 and a half; you'll have to waste 8 bits.)
Looking in the Databook shows that the XCV300 has 16 of them, so you should
be okay. I would suggest instantiating them manually in your VHDL code if
the core generator isn't working for you.
(I've never come to really like the Core generator Myself.)
I've stuck some VHDL code at the bottom of thie post. It's what I used to
create a generic-width RAM structure using BlockRAMs.
All standard disclaimers in effect.
Note: The unisim_nodel library that it refers to is the standard unisim
library, but with all the delays ripped out so that it will simulate
nicely.
Hope it helps.
-Kent
Gerhard Wrote:
>I need to create a RAM in a XILINX-Virtex V300 with the XILINX
>Foundationtool.
>
>My problem is that my RAM has a width of 200 bits.
>
>Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?)
>without a complex addressing.
>
>Futhermore i tryed to create a RAM with the XILINX Coregenerator but i
>got an error message
>
>
>THANKS Gerhard
>
>
--
-- 256 Deep Dual Port RAM based on Xilinx|Virtex BlockRAM
-- Generic WIDTH must be a multiple of 16
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
-- SYNOPSYS TRANSLATE_OFF
library UNISIM_NODEL;
use UNISIM_NODEL.all;
-- SYNOPSYS TRANSLATE_ON
entity BR_DPRAM is
generic (
WIDTH: integer := 16
);
port (
RST: in STD_LOGIC;
-- FIRST port
P0CLK: in STD_LOGIC;
P0ADDR: in STD_LOGIC_VECTOR(7 downto 0);
P0WE: in STD_LOGIC;
P0EN: in STD_LOGIC;
P0DATA_IN: in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
P0DATA_OUT: out STD_LOGIC_VECTOR(WIDTH-1 downto
0);
-- DUAL port
P1CLK: in STD_LOGIC;
P1ADDR: in STD_LOGIC_VECTOR(7 downto 0);
P1WE: in STD_LOGIC;
P1EN: in STD_LOGIC;
P1DATA_IN: in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
P1DATA_OUT: out STD_LOGIC_VECTOR(WIDTH-1 downto
0)
);
end BR_DPRAM;
architecture BR_DPRAM_ARCH of BR_DPRAM is
-- Component declaration of the "RAMB4_S16_S16(RAMB4_S16_S16_V)" unit
-- File name contains "RAMB4_S16_S16" entity: .\src\unisim_VITAL.vhd
component RAMB4_S16_S16
port(
DIA : in std_logic_vector(15 downto 0);
DIB : in std_logic_vector(15 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic;
RSTA : in std_ulogic;
RSTB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
ADDRA : in std_logic_vector(7 downto 0);
ADDRB : in std_logic_vector(7 downto 0);
DOA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector(15 downto 0));
end component;
-- SYNOPSYS TRANSLATE_OFF
for all: RAMB4_S16_S16 use entity
unisim_nodel.RAMB4_S16_S16(RAMB4_S16_S16_V);
-- SYNOPSYS TRANSLATE_ON
signal LOGIC_1: STD_LOGIC;
begin
-- SYNOPSYS TRANSLATE_OFF
assert((WIDTH mod 16) = 0 );
-- SYNOPSYS TRANSLATE_ON
BR_RAM_GEN:
for i in 0 to ((WIDTH / 16)-1) generate
BR_DPRAM_COMP: RAMB4_S16_S16
port map (
-- Port A
DIA => P0DATA_IN( ((i*16)+15) downto (i*16)),
ENA => P0EN,
WEA => P0WE,
RSTA => RST,
CLKA => P0CLK,
ADDRA => P0ADDR,
DOA => P0DATA_OUT( ((i*16)+15) downto (i*16)),
-- Port B
DIB => P1DATA_IN( ((i*16)+15) downto (i*16)),
ENB => P1EN,
WEB => P1WE,
RSTB => RST,
CLKB => P1CLK,
ADDRB => P1ADDR,
DOB => P1DATA_OUT( ((i*16)+15) downto (i*16))
);
end generate;
LOGIC_1 <= '1';
end BR_DPRAM_ARCH;
K. Orthner
enabled, and so on and so forth. but I'm sure that you can fix it up for
your own application.
-Kent
kort...@hotmail.nospam.com (K. Orthner) wrote in
<8F99B20A4kort...@158.202.232.7>:
Ray Andraka
there a reason you can't use 13 block RAMs to get your 200 bit width? Each of
course would need an identical address, which depending on your speed
requirements might dictate duplicated address and control logic. Another
'trick', which is useful if you only need a single port memory and 128 words is
deep enough, is to use both ports to get an effective width of 32 bits. In that
case, you tie the upper address bit on one port to '1' and the same address bit
on the other port to '0'. The remaining address bits as well as the controls
are common, and presto, you've got a single port 32 bitx128 word memory in one
block ram. That will get you up to 256 bits wide in an XCV50, without any fancy
addressing or double access garbage.
I find the COREGen to be more of a hinderance than a help for the BRAMs. It's
not like it adds any useful logic, all it does is instantiate the required
number of BRAMs. I think it is easier, and frankly, more intuitive to just
instantiate the BRAMs directly.
Gerhard Griessnig wrote:
>
> I need to create a RAM in a XILINX-Virtex V300 with the XILINX Foundationtool.
>
> My problem is that my RAM has a width of 200 bits.
>
> Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?) without a
> complex addressing.
>
> Futhermore i tryed to create a RAM with the XILINX Coregenerator but i got an
> error message
>
> Error L-44/C0 : #0 Error:
> D:/programs/xilinx/active/projects/grieda02/ram.vhd line -44 Library
> logical name XILINXCORELIB is not mapped to a host directory. (VSS-1071)
> (FPGA-dm-hdlc-unknown)
> Error L48/C0 : #0 Error:
> D:/programs/xilinx/active/projects/grieda02/ram.vhd line 48 No selected
> element named C_MEM_SP_BLOCK_V1_0 is defined for this prefix. (VSS-573)
> 2 error(s) 0 warning(s) found
>
> Does anyone has an idea, or does anyone has a vhdlcode ?
>
> THANKS Gerhard
>
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email r...@andraka.com
http://www.andraka.com or http://www.fpga-guru.com
Steve Oldridge
those 200 lines from the block Rams to the CLBs for processing is going to be no
mean feat. What are you doing that you need all 200 bits at once? That said, I
can't really think of a way around the problem unless you can do with accessing the
data in chunks (in which case you don't really need a 200 bit wide RAM in the first
place). Just something to consider...
Steve
Peter Alfke
Steve Oldridge wrote:
> I think the real problem you're gonna face is processing those 200 bits... Routing
> those 200 lines from the block Rams to the CLBs for processing is going to be no
> mean feat.
It's not so bad. each BlockRAM has a "vertical" height of 4 CLBs, so the 13 BlockRAMs
have a height of 52 CLBs, of course normally, (in XCV300E or smaller), broken down
into two banks.
Anyhow, there is (nowadays) enough routing for the data.
"This is not your father's XC4025 anymore..."
Peter Alfke, Xilinx Applications
Nicholas C. Weaver
4025? Bah, such a huge waste of silicon. Back when I was an
undergraduate, we had 4003s and we LIKED them. (We didn't like the 1+
hour compile times, however. :)
--
Nicholas C. Weaver nwe...@cs.berkeley.edu
Ray Andraka
them pretty efficiently, and with a little care you can even do it faster than
most people think "real designs" can be clocked.
Steve Oldridge wrote:
>
> I think the real problem you're gonna face is processing those 200 bits... Routing
> those 200 lines from the block Rams to the CLBs for processing is going to be no
> mean feat. What are you doing that you need all 200 bits at once? That said, I
> can't really think of a way around the problem unless you can do with accessing the
> data in chunks (in which case you don't really need a 200 bit wide RAM in the first
> place). Just something to consider...
> Steve
>
> > Gerhard Griessnig wrote:
> > >
> > > I need to create a RAM in a XILINX-Virtex V300 with the XILINX Foundationtool.
> > >
> > > My problem is that my RAM has a width of 200 bits.
> > >
> > > Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?) without a
> > > complex addressing.
--
Gerhard Griessnig
Gerhard Griessnig wrote:
I need a RAM with a deep of 480 (impossible with virtex V300 - so i use for my project the half :240) and a width of 200 bits for implementing a switch for a realtime LAN.
The LAN is developed by us and has a special protokol which requiers 200 bits width packages.
Is it possible to get all 200 bits into a 200 bit shift register in one Cycle (timing)?
THANKS Gerhard
Vhdlcode ?
Ray Andraka
CLB RAM or SRL16's to make up the deficit. at 68 bits per CLB, this is quite
reasonable. If you need speed, the best bet is to use the CLB RAM as a shift
register buffer rather than random access, provided you can come up with a
scheme that works for your design. You'd need about a third of the array (448
CLBs minimum) to make up the deficit. If your logic is not too intense, then
you could probably make that work. If logic an memroy combined is too much,
then you need to go to a bigger device...you can't shove 10 lbs of manure in a 5
lb sack.
As to the getting all the bits into a shift register at once, sure you can. The
shift register will take up 200 luts though. You don't mention what your clock
cycle is. Often, you can use a multiplied clock to take better advantage of the
architecture and thereby shrink the design.
--
Peter Alfke
XCV300E has 32 BlockRAMs, each can be used as 512 x 8.
So if you use all BlockRAMs,you have an array that is 512 deep and 256 wide.
That's more than you need, and you have almost all CLBs left over to do interesting things :-)
( Virtex-E is just "better" than Virtex!)
Peter Alfke,Xilinx Applications
===============================================
Ray Andraka
BRAMs, which only gets him to a depth of 256. My point was if he's not using
all the logic, he could use it to make up the deficit. He'll use up about 1/3
of the CLB's but if that logic is not otherwise used, who cares?
--