Fastest input IOB on a Spartan-3?

[Paul Boven]

Hi everyone,

I'd like to know which input pin/IOB of the Spartan-3 would be able to
toggle (divide by 2) the highest frequency input signal. From earlier
postings by Peter Alfke I understand that not all IOBs are created equal
in this respect, although I don't know how big the differences between
individual IOBs would be. I'm building a frequency counter, and the
higher the input it can handle, the better. What would be the highest
frequency input signal? And which IO-standard to use for highest
performance? Ultimately I will need to design an input
amplifier/discriminator, so input IO-standard is not fixed yet.

Regards, Paul Boven.

[Symon]

Paul,
Probably one of the differential inputs that can feed directly to a DCM. The
DCM inputs have a pre-divide-by-two feature. You should be aware that Xilinx
FPGAs have quite a large input capacitance (~12pF for Virtex II-Pro IIRC)
that you should take into account when trying to match your line to the pin,
especially at the high frequencies you're talking about.
You've considered an external prescaler?
HTH, Syms.
"Paul Boven" <p.b...@chello.nl> wrote in message
news:11259181...@blaat.sara.nl...

[Austin Lesea]

All,

The LVDS input is 5 pF + 100 ohms. Differential input is really two
10pF in series.

So, for highest speed, the differential input is the best.

Austin

[Symon]

All,
Check out the comp.arch.fpga thread entitled "Virtex4 running at 360Mhz DDR"
for a discussion about this stuff. I can't be arsed to explain _again_ that
a 50 ohm line driving 12pF has the same rise time as a 100 ohm pair driving
6pF.
Paul, IIRC, the Spartan parts you mention don't have on-chip resistive (100
Ohm) termination, so you need to provide this externally.
HTH, Syms

"Austin Lesea" <aus...@xilinx.com> wrote in message
news:dfn7t6$60...@cliff.xsj.xilinx.com...

[Austin Lesea]

Symon,

I will be sure not to "arsed to explain _again_" anything from you.

My point is simply that simulation is key to understanding what is going on.

There are no IOs that are any better (or worse) than any others.

If internal 100 ohm termination is available, use it.

Austin

[Symon]

Easy, tiger! No offence intended, I should perhaps have used a less
inflammatory turn of phrase. I was merely trying my best to help the OP and
was a little exasperated that the same confusing point concerning single
ended vs. differential I/O capacitance had arisen once more on C.A.F.

So, I see you say in your last post:-

"There are no IOs that are any better (or worse) than any others."

Yet in your first post in this thread you claim:-

"So, for highest speed, the differential input is the best."

Now, I gather you will no longer be arsed to explain anything to me, (BTW,
many thanks for your help in the past) but would it be possible for you to
clarify to Paul, the OP, how he should resolve these apparently
contradictory statements?

I agree whole-heartedly "that simulation is key to understanding what is
going on". I apologise that I failed to realise this was the point you were
making in your first post. I also apologise for being a sarcastic bastard.
;-)

With tongue firmly in cheek, Syms.

"Austin Lesea" <aus...@xilinx.com> wrote in message

news:dfnrce$3h...@cliff.xsj.xilinx.com...

[austin]

Symon,

Our favorite person makes a really big deal out of the 10 pF IO cap
number. Only he calls it 12 pF (not sure why .... maybe we have a worst
case number somewhere that includes the package C, however the package C
is not a bulk C but a t-line, so that C doesn't count).

It really is 5pF across 100 ohms, but it sounds better to just continue
to pound on 10 pF, as it is confusing enough that some folks will put
all 10 pF across the 100 ohms in their simulations. Or worse yet, they
will add 10 pF to the IBIS when it is already in the receiver model
(single ended) and 5pF differential.

As well, "they" use an external 100 ohms for all their simulations,
where we recommend use of the internal 100 ohms for all high speed
interfaces (really makes things look worse due to the stub).

And, to top it off, they claim an open eye at 1.3 Gbs with really fast
rise and fall times as a good thing.

Well, basically they have to, as they don't have MGTs (in S2), so
anything really fast has to look good and distract you long enough to
think "hey, maybe they really do have something here?"

The fabric can't handle 1.3 Gbs, there is no IP or core for 1.3 Gbs, and
the rise and fall is so fast, that passing RFI requirements will be a
real trick (should radiate like gangbusters).

Really fast rise time more than is needed to support the IO that is
designed to be used on a pin or pins is a real waste. You want 1.3 Gbs?
Do us and yourself a favor, use the MGTs.

Do they have a really fast and clean looking signal at 1.3 Gbs? Sure.
If you think that is an advantage without all the other rather useful
stuff, then be my guest, and go use it. Good luck.

I only fight battles that are worth it, and other than the intentional
misdirection every time I see this, I am just ready to say "if you
believe this is an advantage, go to it."

And, I think you meant "asked" not "arsed."

In good fun,

Austin

[Brian Davis]

Austin wrote:
>
> It really is 5pF across 100 ohms
>

As presently documented in your datasheets and IBIS files, it's
really two 10 pFs in shunt to ground across a 100 ohm +/-20% R.

It may appeal to your inner marketeer to call it 5 pF, but that
won't make your parts work any better.

If you're going to continue to 'correct' folks who quote your
own documentation, at least have the technical honesty to point
out that modeling two shunt C's as an across-the-pair 1/2 C is
ONLY valid if the input signal is perfectly differential.

Here's to hoping that when you eventually publish S3E IBIS and
SSO info, those slimmed-down DCI-less I/O buffers have a lower C.
( And I'd still love to see some of the smaller S3E parts appear
in a ground-paddle VQFP or QFN package )

>
> As well, "they" use an external 100 ohms for all their simulations,
> where we recommend use of the internal 100 ohms for all high speed
> interfaces (really makes things look worse due to the stub).
>

Perhaps you should review your own documentation before throwing
stones at others.

The last time we went round on this, you pointed to the ML450 V4
evaluation board as a shining example of SI design.

If you look at the ML450 schematic, BOM, and board layout, you'll
notice that the HyperTransport input lines are terminated using
external 100 ohm resistors, with stub lengths of about half an inch.

Maybe this was done because you can't meet the HyperTransport +/- 10%
terminator R spec with the _DT terminators, but I'd wager that the
internal R's would work better than those big stubs, especially with
the non-compliant Cin values of your HyperTransport inputs.

I didn't spot any supporting IBIS sims for the ML450 layout anywhere;
perhaps you could publish some 500 MT/s and 1 GT/s simulations in
the user guide, using a fast HyperTransport compliant driver, with
waveforms plotted both at the internal FPGA Rx and at a HyperTransport
bus probe connector on the driving board :)

From HyperTransport 2.0:

internal terminator Rt : 100 ohm +/- 10%

single ended Cin (400-800 MT/s) : 5 pF
single ended Cin (1-2 GT/s) : 2 pF

single ended Cout (400-800 MT/s) : 5 pF
single ended Cout (1-2 GT/s) : 3 pF

Any mention of HyperTransport in your datsheets, app notes, and
user guides should be appropriately footnoted as non-compliant.

Brian

[austin]

Brian,

Thanks for your comments.

All accurate.

Why they The ML450 pcb team) used the external 100 ohms is beyond me.
If we don't meet the C spec, then why bother to be concerned about the R
spec.

You are correct instating the resukts work better with the internal R.

We'd love to "slim down" the IOBs. Anyone have a list of standards that
are useless? Seems like there are a few out there that folks don't use
much, but then again ...

Austin