On Tuesday, June 22, 2021 at 3:18:18 AM UTC-7, Tianxiang Weng wrote:
> On Monday, May 24, 2021 at 3:00:28 AM UTC-7, Tianxiang Weng wrote:
> > On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote:
> > > Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);
> > andrew_b, thank you!!!
> >
> > Weng
Hi,
I now have another similar problem: how to change an integer to a
std_logic_vector.in VHDL-2002.
Here is a code snippet:
signal X :integer range 0 to 15; -- X is used as an index to an array.
signal Y :std_logic_vector(3 downto 0); -- Y is a device input interface so Y data type cannot change, but X may be.
Y <= std_logic_vector(X); -- error!
Thank you.
Weng