Some preliminary help for an FPGA selection

[Dimiter_Popoff]

It will be the first FPGA for me. What I want to do is not complex,
I have done similar controllers (more complex really)numerous times
using logic parts, PLD, CPLD-s etc.
I need to put together a display controller, to just do framebuffer
memory -> display interface. Framebuffer memory will be some sort of
DDRAM (DDR-which depending on the FPGA type), I'll be happy with
a 1920x1080 framebuffer, 32 bits per pixel (likely just 24 will
be used initially). The framebuffer will be updated via PCIe by the
processor so the FPGA has to be large enough to allow me to do
say 2k words fifos for access (2 of them).
How the output will go is unclear yet; probably HDMI (which adds
some complexity of course but looks doable).
The LVDS cable drivers are another unknown - is it a good idea
(if possible at all) to have them on-chip (chip being the fpga)?
Sounds a bit risky but this will not be a consumer product, not
initially at least, so it does not have to be the most abuse
proof unit in the galaxy (but I don't want it to be too easy to
be killed either... I am just looking for people's experience
in the area).
Which way should I go? The tools must be free, I guess this
narrows the choice, we are not a large company.
I will have to do plenty of iterations until I have the thing
work obviously so I want the processor to be able to initialize
the FPGA logic from a file (it has a disk, ethernet, tcp/ip etc.).

I guess I would prefer lower power, too - if I have multiple
choices of similar devices.
From what I saw there are FPGA-s which come with some hardwired
DDRAM interface and PCIe, I'd go for one of these (doing DDRAM
myself sounds like a waste of effort unless it proves necessary,
having to do PCIe myself would probably make me look at other
options).

Thanks,

Dimiter

======================================================
Dimiter Popoff, TGI http://www.tgi-sci.com
======================================================
http://www.flickr.com/photos/didi_tgi/

[Rick C]

I would love to recommend an FPGA for you, but I'm no expert on PCIe or LVDS. They both seem pretty important to your needs.

For low power you might look at a Lattice product. The iCE40 parts are intended for very low power, but might not be enough for your needs. They have the LVDS but I don't recall any PCIe or memory interfaces as hard IP. I'm sure they have an SDRAM interface as a soft core.

They have a variant of the iCE40 line with various hard IP, but I seem to recall it is oriented to some particular interface for embedded stuff, video maybe. I think the name is Cross... something. The iCE40 line has RAM configuration memory with non-volatile backup, one time programmable.

They also have a line of RAM configurable parts not unlike the Xilinx line (that's what it is derived from, the old Orca products licensed from Xilinx by Lucent). I seem to recall they have a new product line in that technology. Lattice is focused on low power, so that might be a good place to start looking.

The tools are free, but you need to obtain an annual license. I guess they want to keep control... which is what they all do, even if you buy a perpetual license. I learned that back when I bought my first Mentor system, circa '90. Even though we paid big bucks for it and the software was usable forever (only the maintenance required annual payments) we had to ask for a license each year.

I only use the tools when I have a current job at hand. It seems I sit down on a Friday night to use the tools and find the license is expired but can't get a new one until Monday! lol They may have automated that so it processes on the weekend, but I'm not sure.

You probably have more interesting things to do on the weekends.

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Rick C.

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The free ISE webpack works with spartan6

[HT-Lab]

My advice would be to download the free FPGA tools (Quartus, Vivado,
Libero, Diamond) first and see which ones offers the high-level (free)
IP you need (PCIe, DDR controller, HDMI, Display controller, FIFO etc).
Then run through a small design to see if you like the IDE, when you are
happy build/simulate/P&R your design and if it is all working (probably
next year) then start looking for a board. There are many to choose from
and some offer a custom route as well if you need it.

Like many FPGA engineers I have a box full of FPGA boards from all
vendors which I bought for "projects" I never completed, the fun part is
always buying the board. I now have the Arduino bug and a second box is
slowly filling up with all sorts of breakout boards....

Good luck,

Hans
www.ht-lab.com

[Michael Kellett]

That sounds like quite an ambitious project for a first FPGA design.
How to go at it depends a lot on your other experience - if you are OK
with designing PCIE and DDRAM hardware, 400+ 0.8mm pitch pin BGA then
working at chip level is OK. If not then use a ready made module with at
least the FPGA, PSU, DDRAM and maybe HDMI on board.

For this I would probably go with Xilinx, Spartan 7 or Artix. The free
tools do a lot, and there is IP for dev boards from Digilent or Trenz
Electronic gmbh.
If you have to pay for Xilinx software it's about £3k for a license ,
updates for a year but it goes on working forever.

I actually prefer Altera or Lattice software to Vivado (its just mind
bendingly complicated - get training - its worth it). Unfortunately the
general support for Xilinx parts (IP, dev boards, general community
help etc) in this area is much better.

There are some nice cheap dev boards for Artix and Spartan 7 (Arty and
Artys7) - we used them (and Digilent Nexus) when we did a an Artix based
design as a sanity checker.

MK

[Michael Kellett]

Oh look, someone has done it all for you already !

(Might be worth a look for ideas - and unless you need quite a few will
be cheaper than rolling your own !)

https://www.aliexpress.com/item/32963893871.html

There are other references on the web, search 'AX7103 fpga'

MK

MK

[Dimiter_Popoff]

Thanks everyone for the pointers and suggestions.
It will take a while of looking and head scratching until I
can say anything with certainty but at the moment I am
looking at spartan 6 and spartan 7 (yet to look at artix).

Looks like spartan 7 does not have a hardwired DDRAM thingie;
how much of a problem will that be?
I have yet to evaluate the tools but I suppose I will be able
to write low level logic, sort of this.d = that.q & whatever,
I have no idea what the syntax will be but I am sure everyone
gets what I mean. Once I am there I'll find my way (and I
fear getting there will not be easy, especially talking to
hardwired stuff like DDR and PCIe).
But "not easy"is not a problem, I fear the "not possible",
especially finding out the latter too late (a friend once quoted
a friend of his - both engineers - about the "oh shit" factor
being applicable to every project; you either say it at the beginning
or at the end... :-).

As you see I am wondering about the basics at this stage,
I'll be grateful for any hints from you people with experience
before I start downloading toolchains and wrestling to
evaluate which and how...

Thanks,

Dimiter

[Rick C]

Try a few simple projects in the tools to see which you prefer. Maybe that won't matter since you seem to be zeroed in on the Xilinx parts.

If you are going to do a serious project, maybe start with a few simple pieces. You can design the RAM interface along with a test bench to test it with. In fact, design the test bench first since that will help you learn about the RAM without worrying about synthesis. Then you can write the RAM interface code and test it to the test bench knowing what you need it to do. This code will need to be synthesizable. That's not a huge issue, but ignoring that in test benches makes them easier to design.

None of this requires hardware or downloading or any of the BS you should not even think about until you have the design fully coded and verified in simulation. I don't know your background, but many software people give short shrift to simulation. In FPGAs it pay huge dividends making debugging 100 times easier than on the bench. I've completed projects that needed hardly any debug time on the bench because the design was 99.99% working after simulation.

Have you picked a language yet? I like VHDL mostly because that is what I'm used to. It is strongly typed, so requires dealing with conversions. It requires you to be explicit so nothing is assumed. Verilog is much less wordy, but has defaults you need to know and understand or it may not give you the results you expect.

I keep saying I'm going to learn Verilog and Linux but never do.

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[jim.bra...@ieee.org]

One choice is to use a small FPGA module with DRAM and other interfaces already provided (along with RTL examples of their usage). The module should use a FPGA suitable to your needs and should be from a vendor that provides long term (several years or a decade or mode) of availability. Then you have a simpler PCB design situation: provide the connectors to plug in the module.

[Michael Kellett]

Xilinx support DD3RAM up to 800MHz on Spartan 7 - it doesn't much matter
to you how much of the support is hard wired and how much is FPGA gates
since you just use their IP (free I think for DDRAM on S7). And you will
use their IP for DDR3RAM because it represents multiple man years of work.

I agree with Rick about the importance of simulation - but I think you
should buy a cheap dev board (like the Arty if you go for Xilinx.)

For two reasons, one because there is quite a lot between a working VHDL
or Verilog simulation and hardware (and its good to learn that from day
1) and secondly because it keeps the interest up when stuff actually works.
(But don't ever bother even trying stuff on the chip until the best
simulation you can do is good.)

MK

[Dimiter_Popoff]

I'd certainly explore such an opportunity if I come across something
like that - which comes with the sources for the fpga etc.

Dimiter

[Dimiter_Popoff]

Thanks Mike,
knowing it does not matter hard or soft DDR was important. I really
don't want to go into implementing DDRAM myself (I would if I had to
but this must have been done by many people already and I don't
need the exercise....).

I am not going to use a board, I never have. It will have to run
on my board anyway, what is key is that I can upload multiple
iterations without wearing out some flash or something; for
the coolrunners I have managed to never damage one, i.e. within
20-30 iterations, that utilizing at times 100% of the cells,
but this is significantly more logic (apart from the PCIe and
DDR interfaces not that much more but well, I can't go without
these two, at least not without PCIe (I could use some static RAM).
At the moment I even don't know how the spartans are uploaded,
is it via jtag or something else (I.e. I have not yet read
much). I will have a few pins of the processor (a t1042) to
jtag the fpga at least for boundary scans, if I cannot upload
it using these well, I'll do what it takes. Key is the processor
being able to upload the fpga with the contents of a file
from its file system.

Dimiter

[Rick C]

You can use JTAG to configure a Xilinx part I'm pretty sure, but they have a configuration interface that can be as simple as four signals. The protocol is very simple but there is little feedback on what is wrong if it doesn't work. The upside is you only have maybe four things to check to be sure it will work.

I went through this once at a company I worked for where four engineers (two were FPGA designers and one was a manager) could not bring up a new FPGA board I designed. I pointed out the handful of things they needed to do and they assured me they had done them all. Then I asked if they did them all at the same time. The guy programming dinked the code to make sure they sent the few extra pulses and the other things and voilà, it worked! I said, "let me know if you need anything else" and went back to my desk. lol It was actually pretty funny, but clearly too many cooks were spoiling that broth.

By any chance are you a software guy? A software guy showed up in one of the FPGA groups some years ago and we all tried to tell him it would be hard to adapt to the differences between sequential languages and HDLs. He said he had tons of room in a spacious FPGA for what he wanted to do and performance didn't matter. So we advised him, the whole time telling him how poorly it would work. In the end he produced very workable code and completed his demo task for a customer.

So I don't tell software guys how hard or different HDL is any more. In reality it's just another programming language. Well, it is a bit different, but not anything a decent teacher can't explain. The guy I learned VHDL from was terrible. On top of that the Orcad VHDL tool was so bad they ended up abandoning it a few months later. lol I switched to the Xilinx provided tool and later had to switch again because Xilinx switched to another brand. Three tools on one project, but I still managed to finish on time.

BTW, that project was my first, but it taught me the lesson of how important simulation is. There were two modes of using the board, recording to the hard drive and playing back from the hard drive, separate configurations, separate designers. I was ready to test on the hardware first and only found a couple of bugs and was done. The other guy took a couple of weeks longer in design and spent a couple of weeks debugging on the hardware. Just one anecdotal example, but I see this over and over. An extra week in simulation saves a number of weeks on the bench.

Simulation is also so much easier than trying to capture signals from inside a chip.

Thanks for listening. I just came in from doing lawn work and this gave me a chance to unwind.

--

Rick C.

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[Michael Kellett]

On 09/08/2020 17:05, Dimiter_Popoff wrote:

snipped

If you don't need the RAM to be that fast or that big then you could use
SDRAM, it'll save you a lot of trouble, both in board layout and FPGA work.

I wrote my own SDRAM controller a long time ago (when quite new to
FPGAs) - not too big a deal at all.

DDRAM is a different thing altogether (reading and writing data in a
300ps window - its a miracle that it ever works !).

Using a pair of 16 bit wide SDRAMs at 100MHz gives you 400 Mbytes/s -
chicken feed by DDRAM standards but maybe enough.

The signals are slow enough for scopes and logic analysers that normal
people can afford.

MK

[Theo]

Michael Kellett <m...@mkesc.co.uk> wrote:
> On 09/08/2020 17:05, Dimiter_Popoff wrote:
>
> snipped
>
> If you don't need the RAM to be that fast or that big then you could use
> SDRAM, it'll save you a lot of trouble, both in board layout and FPGA work.
>
> I wrote my own SDRAM controller a long time ago (when quite new to
> FPGAs) - not too big a deal at all.
>
> DDRAM is a different thing altogether (reading and writing data in a
> 300ps window - its a miracle that it ever works !).
>
> Using a pair of 16 bit wide SDRAMs at 100MHz gives you 400 Mbytes/s -
> chicken feed by DDRAM standards but maybe enough.

Just about - 1080p/60Hz/24bpp is 373MB/s. If you cut the colour depth down
you can reduce that bandwidth.

However you also need bandwidth to write into that RAM - you'll need to
measure how much you need for that.

On PCIe, that means you're in mid-level FPGA territory as it needs high-speed
transceivers. So not the bottom-end Cyclone V E but the fancier Cyclone V
GX. And similar across all the vendors lines - that means you're heading
towards the top end of Lattice's offerings.

One thing to be wary of is that Intel/Altera at least offer time-limited
demos of IP cores that you don't have licences for. The device will work
while plugged into the programmer, but not work standalone. There's
warnings about this, but you may be able to successfully synthesise despite
not having a licence (which might actually be fine for proof-of-concept/eval
purposes).

On the system-on-module front there are lots of vendors but I've personally
worked with https://www.enclustra.com/ who have a decent range, although
possibly higher-end than you want.

For LVDS I'd think about buffering - you might want a proper line driver to
drive a long cable, rather than FPGA I/Os which aren't designed to drive
into a long capacitance. We used a third-party HDMI module once and had a
lot of problems because the registers in the driver chip (made by ITE)
weren't documented - in the end we recorded a log of what the demo code set
registers to and replayed that in the same order in our code, a hack but it
just about worked. Instead of proper HDMI (audio etc) you might think about
DVI-D: HDMI monitors can accept it but it's a simpler protocol. You can
also get chips which take in parallel RGB (6-8 bits per channel), Hsync,
Vsync, pixel clock and output DVI or HDMI. That means you just generate
something that looks like pre-DAC VGA and the chip handles the rest.
You might also consider EDID monitor detection, depending on the
application.

What I'd do is look for a PCIe-card-shaped dev board, which should come with
examples for driving that. For the video side, worst case you can make a
resistive-DAC VGA port off some GPIO pins, but you could look at other
options - for example wiring a parallelRGB-DVI chip off GPIOs. Maybe the
board will come with HDMI or Displayport already (and some demo come), but
that's rare on PCIe-card boards. I think at that point you have to live
with whatever RAM type the dev board gives you - if SDRAM works for
you it'll save some troubles, but I've seen a few where there's only one 16
bit SDRAM, which is low on the bandwidth stakes.

Dev boards sometimes come with a one-seat licence for the tools too.
You might also be able to get access by speaking to a sales rep.

Personally I have a dislike of Xilinx tools and I'd prefer Intel or Lattice,
but I have more experience of Intel in particular, so I may be biased.
On the Intel front, 'Quartus Lite' is the free tools and supports Cyclone,
so I'd be looking at a Cyclone IV or V in GX version. For example:
https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=1159

Meanwhile, in Lattice land (tools licence free only for this board):
http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/LatticeECP3VersaDevelopmentKit.aspx

Theo

[Dimiter_Popoff]

More thanks to everyone for the hints.

Looks like I am going to use some of the Artix devices (Spartan 7
have no PCIe as far as I get it, unless they can do it "soft").
I would not go old style SDRAM, the bandwidth would be limiting
(I need at least twice the bandwidth needed for refresh if the
update via PCIe will work without visible artifacts; much more
if I go to make alpha etc.).
DDRAM3 is fast enough and as Mike suggests at 800 MHz clock
it is a miracle things work but here we are, I have to use that
or fall too far behind. Then there will be DDR-4 or 3l on that
board for the CPU so it has to work anyway.
Last time I used SDRAM was .... 20 years ago, can't really believe
it was that long ago.
http://tgi-sci.com/misc/PICT3084.JPG - another 5 (just 4 mounted)
SDRAMS on the bottom side, 64 bit wide in total - this is the second
board put together, the first one worked for may be 3 months
and fell apart, I had reflown it at least 30 times, was my first
board with BGAs on it).

Doing straight RGB as Theo suggests might come to rescue during
the design of course, but since HDMI is doable it will have to be
done. No MIPI on the agenda yet, they are too secretive so I'll
live without a camera at least initially. Or use a USB one.

I downloaded the VivaLdo (I really spelt it Vivaldo having encountered
the name first just here in Mike's message, got corrected by google...
did not ask for any seasons, luckily :), got a free license for
their webpack. At first glance it looks like it is sufficient and
free but I will not route in an fpga before I have it at least
compile without asking for fees etc., as Hans suggested (or something in
that line). Was an adventure of its own,took about 2 hours to download,
but it seems to work (not that I know yet what the difference is between
vitis HLS, Xilinx Vitis, VivaLdo... DocNav - well, I think I understand
what this is :).

Thanks again for the hints, please keep them coming.
And please keep your thumbs pressed, I have done crazier projects
(at their time) than that (which is by far not just its fpga part),
but I don't know if I still have the drive it takes - hopefully I
can find it.

[Gabor]

PCIe is not something you'd want a soft core for. Spartan7 not only has
no PCIe, it has no high-speed transceivers. Artix-7 would be the better
choice from Xilinx. I believe the tools are better and the cost lower
for a device that has the resources you're looking for. It is supported
by the free tools as I recall. If you go with Xilinx, you'd want Vivado
for this project. Other tools are more oriented toward special
applications like AI (neural networks, deep learning...). Also the
latest tools are really made to support the really expensive newer chips
in the UltraScale++ family or whatever they're up to now.

Good Luck!


--
Gabor

[Rick C]

On Friday, August 7, 2020 at 5:35:32 PM UTC-4, Dimiter wrote:

I remembered the part from Lattice that had the fancy-dancy interfaces, LFD2NX-40. They call it Certus-NX. There are only two sizes and the larger of the two at 39 kLUTs has the hard IP PCIe interface. It's only 1 lane and one controller. It also has SGMII (not familiar with that) with 2x2 lanes maybe. DDR Memory is supported, LPDDR2, DDR3/3L.

--

Rick C.

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[Dimiter_Popoff]

Thanks Rick,
they do look interesting indeed but I saw no mention of a "free
toolchain" so there probably is none (I did not dig though).
I have made up my mind on the Artix device, the webpack tool
says it will do all I need for free (the only downside being
my code will be defacto public but I don't mind that for this
project). So it will be this, I just need a few more weeks to
clear up stuff and dig into that VivaLdo (with or without
the four seasons... :) and do it.

Dimiter

[Rick C]

They are often happy to give out tools. It is possible you might need to talk to a salesperson about the tools for this device. Don't know, I've never bothered with any of the fancy parts.

I'm not clear on the "public" thing. Are you saying Xilinx insists your code be "public"??? Or is this the thing where they want to have access to your code so they can analyze the quality of the tools?

I guess if the "public" thing is a problem the tool can be used when off line and the files can be sequestered on a removable drive when you want to connect to the Internet.

--

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[Dimiter_Popoff]

I refer to their access to the code of course, hence the quotation
makrs. And it does not bother me at all for this project.

I am not sure many toolchains will be happy to work without
internet access nowadays anyway (just my guess).

Dimiter

[Rick C]

Yeah, I expect it was their access you were talking about, but... You never know.

The only Internet access needed for Lattice tools to work is once a year to get the new license file and that can be done by sneaker net if you want.

I've had to work that way before (projects I can't talk about without having to kill you and I don't do wet ware). Then there is the Internet connection I have now going down rather often. We are supposed to soon be getting a new fiber link to the local tower that will solve a lot of our problems. Yea!

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