Can Boundary Scan be used for Analog?

[benn]

As I understand, Boundary Scan compliant devices can be used for to
make sure you don't have any shorts or opens between boundary scan
devices... but what about analog functionality?

For example, if a 1149.1 compliant microcontrollers has a built-in D/
A, can a ATPG test be written such that the full analog swing of the
pin can be tested? Or is TDI/TDO restricted to logic levels only
and arn't meant for analog testing?

If not, anyone know if the new JTAG standards coming down the road
(1149.7, P1587) will have such support? I'd like to use a board test
that actually tests some board functionality logic instead of just
shorts/opens!

[Didi]

On Sep 27, 12:20 am, benn <benn...@hotmail.com> wrote:
> As I understand, Boundary Scan compliant devices can be used for  to
> make sure you don't have any shorts or opens between boundary scan
> devices...

Not really, you can do as much boundary scan operations with a device
as there are implemented into it by the silicon vendor. Typically you
can read logic level at pins and drive to a logic level or tristate
them. Sometimes you can do all that with any pin, sometimes not.

>but what about analog functionality?
>
> For example, if a 1149.1 compliant microcontrollers has a built-in D/
> A, can a ATPG test be written such that the full analog swing of the
> pin can be tested?    Or is TDI/TDO restricted to logic levels only
> and arn't meant for analog testing?

Nothing in the JTAG signals restricts access to some ADC or DAC on
the chip, but I have not seen a chip which does that yet. Which does
not mean there is none, of course; it is most certainly doable over
1149.1.

Didi

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Original message: http://groups.google.com/group/comp.arch.embedded/msg/a3d970f1a122924f?dmode=source