This I/O board was designed several years ago, and worked very well. But
now I get these address conflicts with the new motherboards. Should I
decode the entire 64K address space to make sure my board responds only to
my address selection, or has there been a an industry change in I/O port
address allocation?
Yes you should. Useually the boards use the A6-9 line into a 3 to 8
line decoder. Quickest fix is to use an 8 input AND gate ( for A8-15 )
as the input to the gate pin (most often done with a 74xx30 NOR gate and
a 74xx04 inverter).
As you've obviously noticed an incomplete address decode causes you to
get I/O read/writes at addresses above the A9 line. You are on the
right track.
Have any problems let me know.
Tony Brinlee
AEB, Inc.
tbri...@ix.netcom.com
A good suggestion, and one that I used extensively until I discovered PLA
devices. We're now using a 16V8 or 20Vxx device for address decoding with
a couple of advantages:
1: Single package for all address decoding, with user assignable input and
output pins. Makes printed circuit design much easier, especially on
2-layer boards.
2: enough extra gates to provide buffering for the IO read and write
lines, still in 1 package...
3: can address multiple IO spaces in 1 package, and can provide a range
switch by putting hardware jumpers on a couple of input pins and including
them in the address logic.
4: High input impedance does not load the bus.
Disadvantages: Slightly higher cost compared to 74xx devices and you need
a programmer to tell the chippies what to do... but once you get one,
you'll never go back!
Have fun!
--
car...@teleport.COM God has angels to help with her work,
The devil has politicians
Most of the new motherboards have onboard peripherals (serial, parallel etc)
right in the motherboard chipset. These can clash with your card even if you
have no conflicting ISA cards installed. There are normally CMOS settings
which allow you to control these peripherals (ie. set addresses or even turn
them off completely).
Decoding the whole 16bit IO address space will not resolve a clash as only
A9..A0 (or so) are actually used. At one place I worked, we used the other
address lines for extra addressing. This normally worked OK so long as the
A9..A0 bits didn't clash with other devices. I say "normally" because some 386
memory managers would not support addresses over 3FF in the virtual 86 tables
and the memory manager would throw an exception if we attempted to use any
value other than zero on A15..A10 address bits.
Good luck!
-- Charles
--
_______________________________________________________________
Tony Tyner mailto:tyn...@gte.net http://home1.gte.net/tynerae
Hurco Companies, Inc. (317) 298-2637 x2245
_______________________________________________________________
True. However, many of the motherboards since the early '386 days also
drive the rest of the lines (A10-A15). If they didn't, things like the
new parallel port IEEE-1284 wouldn't work since they rely on the second
`1K bank' of I/O addressing. IBM didn't decode the upper lines on their
old boards, MOST of the plug-in cards don't, but it's required for some.
Just something to keep in mind. It's *not* required to decode the extra
lines, but the addresses ARE available in many machines, nowadays. It's
been a long, slow evolution. In 1980, 1K I/O space was overkill. Today,
I'd be happier with 64K, at least.