single cycle multiplier

[John Smith]

Hi all

I saw a recent post regarding a single-cycle divider (no solutions barring
LUT). It did rekindle a thought: can anyone give links etc. to how a single
cycle multiplier works (as used in most modern DSP chips)?

Thanks
JS

[Andreas Bellgardt]

Hello John!

As I posted above (see single cycle divider) in modern chips this is
achieved by pipelining. I do not agree to do a divider/multiplier with a
huge (about 64kBytes!) lookup table, that is not verry efficient and
normally in production, you have to pay for chip die square.
If you have to design an ASIC/FPGA or CPU core you need a tool like
Synopsis, Xilinx or whatever. With them you get libraries including
single cycle pipelined multiplier/divider and more. So you don't have to
invent something new.

See:
http://www.synopsys.com/products/designware/docs/doc/dwf/datasheets/dw_mult_seq.pdf

Andreas

[John Smith]

Hi Andreas

There must be some other trick that the DSP manufacturers use. I regularly
program DSP chips, but don't recall ever having to flush the pipeline to
wait for the multiplier to spit out its results. Sure, I have to preload the
'feed' registers (called X and Y usually), then issue the multiply
instruction, and the answer appears in the accumulator. No additional cycles
involved.

Some pseudo assembly, no particular processor, but fairly typical code:

r1 = input_vector_address
r2 = coefficients_address

x = *r1++
y = *r2++
acc = 0
repeat loop 10 times:
mpy = x * y || acc = acc + mpy || x = *r1++ || y = *r2++
end loop
acc = acc + mpy

(Chips like Agere DSP16410 can do a line similar to the one in my example,
ie load the X and Y registers, do the accumulation and do the multiply, in a
single cycle (assuming memory locations etc all set up correctly)).

Regards
JS

"Andreas Bellgardt" <bell...@netiera.de> wrote in message
news:b6rgsr$r9g$07$1...@news.t-online.com...

[John Smith]

Scratching around Google, I have found the following link, which mentions
(and gives a circuit diagram) of a thing called a Cascade Multiplier.

http://www.bearcave.com/cae/cascade_mult.html

JS

"John Smith" <som...@microsoft.com> wrote in message
news:b6rdkr$c1j$1...@newstree.wise.edt.ericsson.se...

[Rob Turk]

"Andreas Bellgardt" <bell...@netiera.de> wrote in message
news:b6rgsr$r9g$07$1...@news.t-online.com...

> Hello John!
>
> As I posted above (see single cycle divider) in modern chips this is
> achieved by pipelining. I do not agree to do a divider/multiplier with a
> huge (about 64kBytes!) lookup table, that is not verry efficient and
> normally in production, you have to pay for chip die square.
> If you have to design an ASIC/FPGA or CPU core you need a tool like
> Synopsis, Xilinx or whatever. With them you get libraries including
> single cycle pipelined multiplier/divider and more. So you don't have to
> invent something new.
>
> See:
>
http://www.synopsys.com/products/designware/docs/doc/dwf/datasheets/dw_mult_
seq.pdf
>
>
> Andreas

In a previous life I worked for Intergraph, doing board level repair of
their graphics processors (3 boards with ~500 TTL 74Fxxx chips each...) .
One of these boards contained a single multiplier chip, I think it was from
AMD. It required no pipelines, just two 16-bit inputs and a 32-bit output.
One clock pulse and the result was available. This was back in 1983 or so...
Replacing it required a signature from the manager as it was a *significant*
investment... Another board had a discrete ALU and microcode in 32 ROMs.
Single-stepping through this stuff with a logic analyzer was fun ;-)

Rob

[Unbeliever]

"John Smith" <som...@microsoft.com> wrote in message
news:b6rdkr$c1j$1...@newstree.wise.edt.ericsson.se...

One method is the Wallace tree multiplier (invented back in the 60's by
Prof. Chris Wallace, with whom I had the priveledge of working in the 70's).
It's really nothing new though.

Here's a PowerPoing (ugh!) presentation.

http://www.csse.monash.edu.au/~timf/cse2102/old/ch4.ppt

--
Alf Katz

alf...@remove.the.obvious.ieee.org

[John Smith]

Alf

The Cascade mulitplier reference I found earlier seems to be the same thing.
Thanks for your help

JS

"Unbeliever" <alf...@remove.the.bleedin.obvious.ieee.org> wrote in message
news:3e915112$0$21131$afc3...@news.optusnet.com.au...