Advantages/disadvantages between CMOS/BiCMOS
Mazlaini Yahya
Does anybody know what are the advantages/disadvantages for chips that were designed for target process CMOS or BiCMOS.
Design engineers widely understand that CMOS consumes less power while BiCMOS
eats lots of power but the trade off is that you get extremely high unity-gain
bandwidths.
Are there any convincing advantages/disadvantages on CMOS/BiCMOS?
From a design point of view, what platform should a designer target his/her
design between CMOS and BiCMOS to get the most cost effective chip out of the
two processes.
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James W. Swonger
>Does anybody know what are the advantages/disadvantages for chips that
>were designed for target process CMOS or BiCMOS.
>Design engineers widely understand that CMOS consumes less power while
>BiCMOS eats lots of power but the trade off is that you get extremely
>high unity-gain bandwidths.
>Are there any convincing advantages/disadvantages on CMOS/BiCMOS?
>From a design point of view, what platform should a designer target
>his/her design between CMOS and BiCMOS to get the most cost effective
>chip out of the two processes.
CMOS advantages: low static power dissipation, most advanced feature size
(if you want to push it), largest number of foundry sources, simpler
process architecture usually means lower wafer cost. A very small
geometry CMOS process may be faster in analog applications than a
less advanced bipolar or BiCMOS process (see RF work being done in
CMOS-only processes - Berkely?)
CMOS disadvantages: No bipolars, some circuits not practicable or more
difficult to implement
BiCMOS advantages: richer device set. Bipolars are easier to make high
frequency analog circuits, precision references, low-offset amplifiers
with. And you can always constrain yourself to only use the CMOS if
you're trying to keep static power down. CMOS circuits at speed may
have more total losses (capacitance is higher) than bipolars. May
allow more compact circuits for some types.
BiCMOS disadvantages: More complex process, higher wafer cost, probably
less advanced lithography (process probably took longer to get up and
running since there were more device types to global-optimize).
Since you can use the CMOS in either case, designers would generally opt
for the greater up-front design freedom. Meanwhile whoever's holding the
money bag will press for straight CMOS implementations. If you know the
circuit functional content you can make a more considered choice. There
is no generalization that works - else why would there be options?
--
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Tom Knight
> From: j...@billy.mlb.semi.harris.com (James W. Swonger)
> Newsgroups: sci.electronics.design,sci.electronics.misc,sci.electronics.cad,sci.electronics.components,sci.electronics.repair,sci.engr.semiconductors,comp.arch.fpga,comp.arch.embedded
> Date: 7 May 1997 13:25:37 GMT
> Organization: Harris Semiconductor, Melbourne, Florida
>
> >Does anybody know what are the advantages/disadvantages for chips that
> >were designed for target process CMOS or BiCMOS.
An important issue which was left out of the previous list is the
scalability of the process to smaller feature sizes (and therefore
lower voltages). Right now, a .25 micron process really wants to run
at about 2.5 volts or less; as we scale to .15 or below, the voltages
continue to go down.
Unfortunately, the Vbe of bipolar devices does not scale with
dimension, but remains a constant (roughly) since it depends on the
log of the doping concentrations and the temperature.
So, since for most bipolar circuits we need 5Vbe to 3Vbe of power
supply voltage, and Vbe is about 0.75 volts, we have a severe
conflict.
BiCMOS thus has a very limited life span, due to scaling laws.
Do your design in pure CMOS and take advantage of the next 15 years of
scaling.
Note that this is what Intel is doing, as opposed to what they were
saying three years ago, when BiCMOS was the "killer technology" which
would soon wipe everyone else off the map. Anyone with a half decent
process oriented education knew this was BS then, but the trade and
financial press thought it was great.
Homework: Compare and contrast Exponential.
Oliver Bartels
In <5kpvsh$i...@hearye.mlb.semi.harris.com>, j...@billy.mlb.semi.harris.com (James W. Swonger) writes:
>>Does anybody know what are the advantages/disadvantages for chips that
>>were designed for target process CMOS or BiCMOS.
Additional BiCMOS advantage (*the* advantage) :
BiCMOS digital outputs, whether internal or external, are faster compared to
regular CMOS outputs because a MOSFET channel limits the available current
for charging/discharging the (parasitic) capacity connected to the output by
the load. A bipolar/MOS combined stage can handle such peak currents faster
than a pure MOS stage.
Greetings Oliver
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Oliver Bartels + Erding, Germany + obar...@bartels.de
http://www.bartels.de + Phone: +49-8122-9729-0 Fax:-10
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David McClanahan
In article <5km8gv$j...@ms.mimos.my>, mazl...@ms.mimos.my says...
>
>Does anybody know what are the advantages/disadvantages for chips that were
designed for target process CMOS or BiCMOS.
>
>eats lots of power but the trade off is that you get extremely high unity-gain
>bandwidths.
>
>Are there any convincing advantages/disadvantages on CMOS/BiCMOS?
>From a design point of view, what platform should a designer target his/her
>design between CMOS and BiCMOS to get the most cost effective chip out of the
>two processes.
>
>
>
>Please visit : http://www.jaring.my/mimos/bi/rd/icdc/icdcprof.html
>
>*******************************************************************
offsets. In general bipolar transistors have better matching charactoristics.
CMOS output stages are better for "rail to rail" operation and CMOS inputs have
lower input bias currents. It just depends on what your trying to achieve.
Dave