Currently I have my eye on the XSA-50 from Xcess because it has a fpga and a
cpld and ram and flash
( http://xess.com/prod027.php3) - What can you fit in a 50k gat FPGA - A
processor, memory controller, video and io support?
A am also interested in FPSLIC but I understand you can only use the tools
for 4 months and then they cost many $$$$ after that
Are there any other boards that anyone can suggest that are reasonably
prices and include tools. Does anyone have any comments on either of these.
Thanks for any advice
You can get lots of the tools for free these days, such as WebPACK from
Xilinx, etc. but if you want to do your own processors, you probably need a
good VHDL simulator, which might be not easy to find cheap...
"Ralph Mason" <masonralph_at...@thisisnotarealaddress.com> wrote
in message news:SAlr9.7941$Os6.1...@news.xtra.co.nz...
- 200k/50k gate Spartan-II FPGA
- Download cable included
- ISE Webpack included
- Bundles with Ram and Flash available
Ralph Mason schrieb:
50k is very tight for that. You may succeed, but the processor will be a
small one (8bit risc), and the video support something like a simple LCD
> A am also interested in FPSLIC but I understand you can only use the tools
> for 4 months and then they cost many $$$$ after that
Atmel offers 6 month of free license if you write an appnote for them. They
are not too responsive when reviewing appnotes, though, so don't rely on it.
You may opt for the AT40k FPGA though, with free software download. But to
be honest, I'd rather recommend you to take the convenient route (XILINX) when
you just want a vanilla FPGA without special features. The smaller vendors
sometimes have quirks in the toolchain without fix available.
If you know what you are doing, you can fit eight 16-bit RISC processors in
50K gates FPGA, e.g. a XCV50E. See www.fpgacpu.org/log/nov00.html#001115.
The XC2S50 in the XSA50 offers the same number of LUTs, but half as much
BRAM, as an XCV50E, however, but you can still fit four processors and have
half the FPGA free for peripherals.
See also my Circuit Cellar article series, Implementing a RISC System in an
FPGA, for a description of an SoC with a pipelined 16-bit RISC, on-chip bus,
and a video controller, in a "5,000" gate XC4005, at
Jan Gray, Gray Research LLC
> > What can you fit in a 50k gat FPGA - A processor, memory controller, video
> > and io support?
> 50k is very tight for that. You may succeed, but the processor will be a
> small one (8bit risc), and the video support something like a simple LCD
The 6502 core that you can license from WDC is 3K gates. Even an 8086 is under
Digital design from conception to production
> jetmarc wrote:
> > > What can you fit in a 50k gat FPGA - A processor, memory controller, video
> > > and io support?
> > 50k is very tight for that. You may succeed, but the processor will be a
> > small one (8bit risc), and the video support something like a simple LCD
> > controller.
> The 6502 core that you can license from WDC is 3K gates. Even an 8086 is under
> 20K gates.
The NC4016 Forth Chip was only 4000 gates for a 16 bit microprocessor.
Ice cold running at 10MHz intensive processing.
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Well, then I ask myself why I have such difficulties fitting small micros
into 50k FPGAs?
Maybe you're right, my current design with 8 multithreaded 1-bit controllers
synthesizes to only 560 gates according to statistics. However, it barely
fits into a 40k device and neads manual tuning in the place&route tool chain.
With peripherials, I'm at 50% logic usage and 75% block ram usage.
Does the 3k 6502 actually fit into a 5k device? The forth chip fits into
a 5k or 10k device? I'm impressed.
What am I doing wrong?
When comparing to "ASIC gates" e.g. NAND gates, as Alfke writes, " Assume
that every LUT is worth 6 gates and every flip-flop is worth 6 gates, then
every Logic Cell is worth 12 gates (sometimes more, sometimes less)."
As my piece shows, in the XC4000/E days, Xilinx counted each logic cell
(LUT+FF) as about 12 NAND gates. Then Xilinx marketing got into the act,
counted on-chip distributed select RAM (LUT RAM) as RAM (where one LUT = one
16x1-bit SRAM = a great many NAND gates), and approximately doubled their
gate count per LUT. Then with Virtex (and thence Spartan-II) they added
block RAM, and started adding some utilization of *that* to the gate count,
now relabelled "system gates". Then with Virtex-II, the block RAMs grew
bigger and again so did the "system gate" count.
So today a modern XC2V1000, a "1,000,000 system gate" FPGA, has about 10,000
LUTs, and by the old 12 gates/LUT+FF formula, can absorb a (zero RAM, half
flip-flops) ASIC of about 120,000 NAND gates.
Similarly, the XC2S50 under discussion has 16x24 CLBs * 4 LUTs+FFs/CLB =
1536 LUTs+FFs. At 6 gates/LUT and 6 gates/FF, it can absorb about 9200 NAND
gates of random logic and another 9200 NAND gates of flip=flops. Xilinx
calls it a 50,000 gate part because if you use some of the block RAM and LUT
RAM you can indeed handle a bigger circuit than an equivalent 50,000 gate
It all comes down to what you're mapping into the device. If you have more
than 10,000 NAND gates of random logic, not counting flip-flops, it might be
a very tight fit indeed, in a 50,000 gate part.
A heavily-optimized, hand-technology-mapped, hand-floorplanned, pipelined
16-bit RISC, including 1/2KB or 1KB of SRAM, fits in about 1/8 of this
device, but would not fit in a 6250-NAND-gate ASIC.
If you design your circuits to take good advantage of the FPGA, use FPGA
device idioms, design in terms of 4-input lookup tables, use LUT RAM, use
technology mapping tricks to merge adders and muxes, use FFs, use FF
clock-enables, use TBUFs, etc., then you can squeeze quite a lot of
functionality into a "50,000 system gate" FPGA. See also my DesignCon 2001
paper "Designing a Simple FPGA-Optimized RISC CPU and System-on-a-Chip"
In particular, regular pipelined RISCs are often quite a bit smaller than
irregular legacy 8-bit MCUs. As I wrote (fpgacpu.org/usenet/homebrew.html)
"It is amazing what you can squeeze onto these parts if you design the
machine architecture carefully to exploit FPGA resources. In contrast,
there was a very interesting article in a recent EE Times by a fellow from
VAutomation doing virtual 6502's in VHDL, then synthesizing them down into
arbitrary FPGA architectures. Although the 6502 design used only about 4000
"ASIC gates" it didn't quite fit in a XC4010, a so-called "10,000 gate"
FPGA. That a dual-issue 32-bit RISC should fit, and a 4 MHz 6502 does not,
states a great deal about VHDL synthesis vs. manual placement, about legacy
architectures vs. custom ones, and maybe even something about CISC vs.
Well admittedly the NC4016 was never placed in a FPGA. It was an ASIC and
it is, sadly, no longer made. Harris took over the basis of the design for
the RTX2000 series and the gate count went up as they put 512 cells of
Stack Memory onboard (Return Stack Cells were 21 bits Parameter Stack
cells were 16 bit). Stack machines are a worthwhile area to look at if
you want efficient processing. Try looking at the Ultra Technology
Website for links to FPGA based processor projects (link is from the
bottom of my Forth page - see sig).
I got a Java processor (http://www.jopdesign.com/) running on an Altera ACEX
1k50 and thats a 32 bit processor :-)