6-layer board help...
Erwin Torbeyns
Jacob W Janovetz <jano...@coewl.cen.uiuc.edu> wrote in article
<5u1jm7$l1g$1...@vixen.cso.uiuc.edu>...
> Hello,
>
> I'm doing a 6-layer board and am wondering where the inner layers
> go. I've seen many boards where the inner layers are visible from the
> outside. Do they go closest to the surface or inside the power/ground
> layers?
> If both are acceptable, what are the benefits of each? The six
> layers are only used in digital areas and maximum clock speed is
> about 66-80MHz in some areas.
There is much discussion about this. Do we put the power/ground layers on
the outside with the signal layers between, or do we put them both inside,
closest together with the signal layers on the outside ?
I think they both have advantages.
Some prefer the power/ground on the outside, so they will shield the signal
layers. So the signals will not radiate perpendicular to the surface, but
only in the same plane.
I have doubts about this improving much on EMC radiation, since i believe
the power planes also will radiate.
Others prefer the power/ground inside and close together, because it will
reduce the high frequency noise on the power (capacitor effect) and improve
signal quality (crosstalk).
I used the last aproach on a 4-layer design (power/ground on inside, signal
outside) 40 MHz clock, 20 Mhz bus speed. Not so much that i believed it was
best, but it's nice when you still can access the signal traces on a
prototype design. Because of the digital design and high speed i was
worried about EMC radiation. But it turned out to be better than expected.
Erwin.
Don North
In article <5u1jm7$l1g$1...@vixen.cso.uiuc.edu>, jano...@coewl.cen.uiuc.edu (Jacob W Janovetz) wrote:
> I'm doing a 6-layer board and am wondering where the inner layers
> go. I've seen many boards where the inner layers are visible from the
> outside. Do they go closest to the surface or inside the power/ground
> layers?
> If both are acceptable, what are the benefits of each? The six
> layers are only used in digital areas and maximum clock speed is
> about 66-80MHz in some areas.
You can do the stackup in a number of ways, but the most typical would be either
(1) sig1/sig2/vcc/gnd/sig3/sig4,
(2) sig1/vcc/sig2/sig3/gnd/sig4,
or (3) vcc/sig1/sig2/sig3/sig4/gnd.
Option (1) is the older way, so that all inner signal layers can be 'seen' and reworked if necessary (I've cut inner layers with a sharp knife and a steady
hand; it can be done if need be). Downside is impedence is less controlled.
Option (2) is somewhat better electrically in that all layers are the same distance from a power/ground plane (better impedence control, especially in the inner layers).
However, forget about reworking an inner layer signal. Only put nets there that you
'know' are correct and will never change :-).
Option (3) is for those real paranoid about EMI/RFI emissions, and would like better
impedence matching on all layers (all are stripline). But don't do this one until
you are real sure of your design; it is virtually unchangeable. Also good for
hiding the interconnect of your design to the passive observer, should you be so
inclined. Or at least make it much harder to figure out.
Personally for the design you seem to be contemplating option (1) will probably
be more than adequate electrically with the added advantages I mention above.
That's the option I'd pursue if I were you.
---------------------------------------------------------------------------
Donald N. North KD6JTT don....@technologist.com
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
{{{{{{{{ Facts are facts, but any opinions expressed are my own }}}}}}}}}
---------------------------------------------------------------------------
Jim Thomas
Jacob W Janovetz wrote:
>
> Hello,
>
> I'm doing a 6-layer board and am wondering where the inner layers
> go. I've seen many boards where the inner layers are visible from the
> outside. Do they go closest to the surface or inside the power/ground
> layers?
> If both are acceptable, what are the benefits of each? The six
> layers are only used in digital areas and maximum clock speed is
> about 66-80MHz in some areas.
Usually the power and ground planes go on the innermost layers of the
card. This helps if you need to cut a trace on an inside layer because
you can see it (you can't see though solid copper... unless you have a
large "S" on your chest).
I don't think you can put the power and ground planes on the surface
layers - that would preclude (or at least complicate) the use of surface
mount components.
You could also sandwich a noise-sensitive layer between power and
ground, but I don't know how much this "shield" really helps/hurts.
One other note... the trace impedence is affected by the distance
between the trace and the power/ground plane. It can vary from (I'm
guessing...) under 25 ohms to over 100. The farther away from the
plane, the higher the impedence. That's why it's good to keep a trace
on the same layer, and if you have to change, try to keep the distance
to the planes constant. Drastic impedence changes cause reflections at
high speeds.
I hope this helps. It's been a long time since I thought about any of
this, and I'm sure others out there are more knowledgable.
--
-jwt 8)
========================================================================
| Work: jth...@fallschurch.esys.com Home: vath...@erols.com
| Good judgement comes from experience.
| Experience comes from bad judgement.
| Opinions expressed here are Jim's and may not be those of his employer
========================================================================
Tim Tait
How is option (3) any better than (1) for controlled impedances?
Also not mentioned:
- options 1/3 allow for significant possibilities of crosstalk on the
signal layers, if any routing parallelism is present on layers not
seperated by a Vcc or Gnd plane.
- options with gnd/vcc closer to surface allowing for better thermal
conduction from components to planes via vias.
Don North wrote:
>
> In article <5u1jm7$l1g$1...@vixen.cso.uiuc.edu>, jano...@coewl.cen.uiuc.edu (Jacob W Janovetz) wrote:
> > I'm doing a 6-layer board and am wondering where the inner layers
> > go. I've seen many boards where the inner layers are visible from the
> > outside. Do they go closest to the surface or inside the power/ground
> > layers?
> > If both are acceptable, what are the benefits of each? The six
> > layers are only used in digital areas and maximum clock speed is
> > about 66-80MHz in some areas.
>
> You can do the stackup in a number of ways, but the most typical would be either
> (1) sig1/sig2/vcc/gnd/sig3/sig4,
> (2) sig1/vcc/sig2/sig3/gnd/sig4,
> or (3) vcc/sig1/sig2/sig3/sig4/gnd.
>
> Option (1) is the older way, so that all inner signal layers can be 'seen' and reworked if necessary (I've cut inner layers with a sharp knife and a steady
> hand; it can be done if need be). Downside is impedence is less controlled.
>
> Option (2) is somewhat better electrically in that all layers are the same distance from a power/ground plane (better impedence control, especially in the inner layers).
> However, forget about reworking an inner layer signal. Only put nets there that you
> 'know' are correct and will never change :-).
>
> Option (3) is for those real paranoid about EMI/RFI emissions, and would like better
> impedence matching on all layers (all are stripline). But don't do this one until
> you are real sure of your design; it is virtually unchangeable. Also good for
> hiding the interconnect of your design to the passive observer, should you be so
> inclined. Or at least make it much harder to figure out.
>
> Personally for the design you seem to be contemplating option (1) will probably
> be more than adequate electrically with the added advantages I mention above.
> That's the option I'd pursue if I were you.
>
> ---------------------------------------------------------------------------
> Donald N. North KD6JTT don....@technologist.com
> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
> {{{{{{{{ Facts are facts, but any opinions expressed are my own }}}}}}}}}
> ---------------------------------------------------------------------------
--
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Don North
In article <340B9B0D...@mediaone.net>, Tim Tait <nos...@mediaone.net> wrote:
> How is option (3) any better than (1) for controlled impedances?
Simple; the outer traces are microstrip (ie, half the dielectric is air,
half is PCB material) while buried traces are stripline (all dielectric
is PCB). Outer traces are lower propagation delay (faster) as well as a
different impedence than inner traces, given the same trace width and
height factors. Important in some applications, not so in others. In
option (3) all traces are stripline (same prop delay), but impedence
does vary where sig1~sig4 and sig2~sig3 in either (1) or (3).
> Also not mentioned:
>
> - options 1/3 allow for significant possibilities of crosstalk on the
> signal layers, if any routing parallelism is present on layers not
> seperated by a Vcc or Gnd plane.
Typically one uses adjacent layers for routing in different directions
(ie horz-mostly vs vert-mostly layers) so same-layer crosstalk due to
parallelism is usually more of a concern. If impedance control and
crosstalk is truly a concern; then the best practical option is:
(4) .../gnd/sig/sig/gnd/sig/sig/gnd/...
This produces constant impedance across all inner signal layers as
well as minimal crosstalk if pairs of adjacent inner signal planes
run in perpendicular directions.
> - options with gnd/vcc closer to surface allowing for better thermal
> conduction from components to planes via vias.
Most thermal conduction goes thru IC leads or thru specific metal contacts
placed on the package body. For IC lead conduction into the power planes,
distance to the plane is not an issue that really matters; the few extra
10s of mils of spacing is not significant. Power planes are not very good
heat sinks for high power devices (radiating body is too small) so larger
air-cooled multi-finned external metal heat sinks are much more effective.
My original recommendation still holds that the original poster goes with
option (1) (simple sig1/sig2/pow/gnd/sig3/sig4) since he was not pushing
the envelope at all and required a simple prototype solution.