Fwd: INTRODUCTION- Campus Placements -- Cadence Design Systems, Pune (Tensilica)
Abhishek Vanjari
From: "plac...@coep.ac.in" <plac...@coep.ac.in>
Date: May 22, 2014 2:47 PM
Subject: INTRODUCTION- Campus Placements -- Cadence Design Systems, Pune (Tensilica)
To: "coep...@googlegroups.com" <coep...@googlegroups.com>, "btech" <bt...@coep.ac.in>
Cc: "Gauri Deval" <gde...@cadence.com>
Dear Students;
Pls find enclosed herewith a brief introduction of Cadence Design Systems, Pune (Tensilica).
Interested Students from UG/PG of EXTC, Comp;Instru. Electrical to apply to placement cell.
Contact (Office) 020-2550 7022, 2550 7023.
Sent: Thursday, May 22, 2014 11:11 AM
To: plac...@coep.ac.in
Subject: Campus Placements -- Cadence Design Systems, Pune (Tensilica)
Hello,
As discussed on Monday, May 19th, sending you the details of work profile and a brief description about our Organization.
About Cadence
Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.
Cadence is an equal opportunity employer and is committed to hiring a diverse workforce. Current employee headcount is 6000 across the globe.
About Tensilica
Tensilica's DSP processors are based on the proven Xtensa architecture and are configurable with two unique features:
Configurability - designers are offered a menu of checkbox and drop-down menu options so they can pick just the features they need
Extensibility - designers can add multi-cycle execution units, registers, register files, and much more using the Tensilica Instruction Extension (TIE) methodology, where the designer only has to specify and verify the functional behavior of the new data path and the RTL and the complete software tool chain including the ISS, C-compiler, Debugger, RTOS components etc are automatically generated.
Design Verification / Hardware
Position Description:
● As a member of the Design Verification Team for Xtensa processors you will be responsible for verification of microprocessor cores and their peripherals.
● Under the mentor-ship of a verification designer, you will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
● You will also assist with developing test plans, debugging failures and analyzing coverage information.
● You will work closely with the RTL and EDA teams.
DSP
Job Description
This job involves the development of DSP processors cores for signal processing algorithms. This involves:
● Developing and testing customized instructions for accelerating signal processing algorithms. using the TIE language.
● Developing, debugging and optimizing examples and software libraries
● To make sure that the customized instructions are optimized considering hardware gate count & power and verification of the customized instructions.
● Generating the engineering and customer documentation.
Regards
HR
Cadence Pune (Tensilica)
You received this message because you are subscribed to the Google Groups "COEP Training and Placement 2014" group.
To unsubscribe from this group and stop receiving emails from it, send an email to coeptnp14+...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.