Re: Doubt in VHDL for "generic map (7)" statement given in "register" vhdl program

[Shampa Chakraverty]

Dear Tarun and others (many may be having same doubts)

I know it is all a bit confusing. The result of making IEEE standards (the guiding principle of standardization is : include all possibilities and incorporate maximum flexibility). 

Let me try. First just note that an entity can be tied to any architecture. Further a component can be tied to any entity-architecture pair. 

1. The generic value in the ENTITY is the global default value. If there are no generic value given in the architecture, then this default will be used.

 

2. You get two chances to override this default. One is when a component is declared in the declarative section of the architecture. This is a sort of local default. All instantiations of this component will use this local default. 

3. Usually however, this local default is the same as the global default of the entity for that component (NOT the test bench's global default). 

4.  This local default can be further overloaded when the component is being instantiated by generic map and port map. Each instantiated component can therefore have its own generic value. 

5. So that raises a question: why should the test bench have a global default at all, since all components and their instantiations have their own values?

Reason is the signals of the testbench. They cannot override generics and therefore must be handed down a default value. 

If there are doubts still, hv calrified in col

B'luck

On Sat, Oct 20, 2012 at 1:48 PM, Tarun Gehlaut <tarun....@gmail.com> wrote:

Ma'am I was analysing the VHDL programs you had sent us.

In the main declaration of the entity "regn" we have made N as 4.
Later in the "testbench" initially for entity "tbregn" we make N as 7 and when regn component is added to the testbench we declare N as 4.
I agree that both these N work differently.
However since here we have only one component in the testbench, shouldn't N for both be same(as the main purpose of N here is to define the size of input and output "std_logic_vector".
If there were more than one component we could have said that some signals of the testbench were connected to one component and some to the other, so the difference in the value of N for testbench entity and regn entity. But why are they different here?

Plus there is the statement "generic portmap(7)". Does this statement change the generic N of the component inside the testbench to 7 meaning changing the value of N from 4 to 7 for regn?

Also since the input is given in hexadecimal (X"00") when we are writing the stimulus process. My doubt continues on the fact that since inpt lines are 5(4 downto 0) how can give input as 8 lines? 

-----TEST BENCH-------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
 
ENTITY regntb IS
generic (N:natural:=7);
END regntb;
 
ARCHITECTURE behavior OF regntb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT regn
	 generic (N: natural:=4);
    PORT(
         regin : IN  std_logic_vector(N downto 0);
         regout : inOUT  std_logic_vector(N downto 0);
         reset : IN  bit;
         incr : IN  bit;
         clk : IN  bit;
			load: in bit
        );
    END COMPONENT;
    

   --Inputs
   signal regin : std_logic_vector(N downto 0) := (others => '0');
   signal reset : bit := '0';
   signal incr : bit := '0';
   signal clk : bit := '0';
   signal load: bit := '0';

   --Outputs
   signal regout : std_logic_vector(N downto 0);

-----clock time period
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate DUT
   dut: regn generic map (7) PORT MAP (
          regin => regin,
          regout => regout,
          reset => reset,
          incr => incr,
          clk => clk,
	 load =>load
        );

--
Regards

Tarun Gehlaut
Third Year Undergratuate
Department Of Computer Engineering,
Netaji Subhas Institute of Technology
Dwarka, New Delhi
Ph: +91-9868733361

--
____________________________
Dr Shampa Chakraverty
Professor & Head, Deptt. of Computer Engineering
Netaji Subhas Institute of Technology
Dwarka, Sector 3, New Delhi-110078
Phone: 91-011-25099062(O)
09899568694 (M)

[Tarun Gehlaut]

Thank you ma'am
It did solve my doubt.