Processor design in vhdl

[Shampa Chakraverty]

Dear students,

Hope you have experimented with registers. With generics you can instantiate registers of any width.

As components of the processor, you need to implement the following. Refer 'Ckt deisgn with vhdl  By Volnei A. Pedroni' for guidelines. But note that you may have to alter the design to suit yr requirements. 

Also it is better to use generics. This allows circuits of any width to be instantiated. This is called parameterized deisgn.

1. For hardwired control, you need 

1.1 A sequence counter. See page 95. Make in modulo 16 (or modulo N) and also add a start signal. The processor starts working only when start is ON.

1.2. You need a decoder to decode the opcode as well as the sequence counter. See page 56. Here a bin-2-integer conversion is used to activate the needed output. 

    However, you can use the case statement to make explicit all cases. For example for 2 to 4 decoder in process style

    case (sel) is 

        when "00" => outp <= "1110";

         when "01" => outp <= "1101";

        when "10" => outp <= "1011";

        when others => outp <= "0111";     --note OTHERS in the last case. It is essential. Why?

  end case;

   

    You can also implement the decoder in concurrent style. In that case, use the with statement (refer book) 

1.3. You need multiplexers. See page 72

1.4. You need gates to generate all control signals 

1.5 In case you want to try out microcoded control unit, you will need a ROM (page 221), Mux, rControl register, a Subroutine register and some other gates. 

       Also, you have to write the microcode. 

2. For data path, you need registers and the ALU besides internal busses. 

2.1 Registers: we have done before

2.2 ALU See pages 76-78.

2.3 Internal busses -data bus, address bus and control lines. Use signals.

2.4 You also need a shift register - in fact the ALU is a multi-purpose register. See page 150 for guidelines. The ALU design is particularly tricky. It needs a parallel load 

       facility, a shifting facility, increment, clear, Output enable. It must be one of the inputs of the ALU and also receive its output.   

3. The memory unit: The RAM is needed. See Page 223. Modify it so that it has a chip enable, separate RD and WR inputs. Also make generic (or 4K of 16 bits as in Mano).

4. Finally, you must connect all the above components using structural style. 

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____________________________
Dr Shampa Chakraverty
Professor & Head, Deptt. of Computer Engineering
Netaji Subhas Institute of Technology
Dwarka, Sector 3, New Delhi-110078
Phone: 91-011-25099062(O)
09899568694 (M)