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SMP BARRIER PAIRING
-------------------
When dealing with CPU-CPU interactions, certain types of memory barrier
should
always be paired. A lack of appropriate pairing is almost certainly an
error.
A write barrier should always be paired with a data dependency barrier or
read
barrier, though a general barrier would also be viable. Similarly a read
barrier or a data dependency barrier should always be paired with at least an
write barrier, though, again, a general barrier is viable:
CPU 1 CPU 2
=============== ===============
ACCESS_ONCE(a) = 1;
<write barrier>
ACCESS_ONCE(b) = 2; x = ACCESS_ONCE(b);
<read barrier>
y = ACCESS_ONCE(a);
Or:
CPU 1 CPU 2
=============== ===============================
a = 1;
<write barrier>
ACCESS_ONCE(b) = &a; x = ACCESS_ONCE(b);
<data dependency barrier>
y = *x;
Basically, the read barrier always has to be there, even though it can be of
the "weaker" type.
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