SFU ID: tliaqat
Github username: tliaqat
Line and file: lines 27-49, trans.c
Expected behavior: 32x32: 5/5, 64x64: 5/5
Observed behavior: 32x32: 4.8/5, 64x64: 4.2/5
Question: I've implemented the blocking method to get my test-cases most of the way there. But any extra strategies I try either don't affect the number of misses or increase the number of misses. Are there any hints that can point me in the right direction to erase the last few cache misses?