JAL Instruction Bits

[Hareet]

Week : 5

Slide deck name: L10-Assembler-Linker

Question: 

In the Linker Example: Resolving an External Fn Call, after the unresolved reference to printf is resolved, any "JAL, printf" instructions in the .text of the final executable contain 0x40023CEF. 

My understanding is that 0xEF consists of 1110 1111, where the lowermost 7 bits are the JAL opcode and so the MSB (0b1) must refer to reg x1 as the rd. The remaining 6 bytes then contain the absolute address of printf: 0x40023C. 

What's confusing me is that this doesn't follow the instruction convention laid out on the RISC-V card. Is this just an example to help our understanding of linking and not representative of the actual instruction bits?

[Arrvindh Shriraman]

Not sure what you are confused. Your understanding of the instruction is correct.

Printf is located at absolute address 0x40023C and jal is simply going to jump to it, while saving in x1 (pseudo name: ra) PC+4.

[Hareet]

According to the RISC-V card and how we parsed instructions in A2, after the opcode's 7 bits, rd should be 5 bits (in this case , 00001 for reg ra) and the remaining 20 bits is the immediate which is an offset, not an absolute address. So on the 2nd pass by the assembler, any "JAL, printf" instructions would be filled with the relative offset to printf from each respective instruction address. But the instruction bits in the above example don't follow this convention. 

[Arrvindh Shriraman]

Ah; yes you are correct. That offset should have been recalculated and permuted, but I had left it as it is to help the reader understand.

I will add a note; thanks.

[Hareet]

Thank you for the help!