port and node name conventions

[Geoffrey Coram]

In
In an e-mail discussion prior to the creation of the subcommittee,
one member suggested:

1. Verilog-A compact model port number and order should following
device terminal convention, like MOSFET has only 4 terminals,
the order should be always (D G S B).

2. It is also suggested to use conventional internal node name for
Verilog-A. Like "int_d" (internal drain), "int_s" (internal source)
for MOSFET, etc. The compiler is easier identify internal node for
better optimization.

I assume point 1, would be adjusted for a MOSFET with a thermal
terminal, or for an SOI model that has a body node that is
distinct from a possible external body contact (eg, BSIMSOI,
whose fourth terminal is "E", and the B terminal is an optional
5th or 6th).

For point 2, BSIM4 has 2 internal gate nodes and 3 internal body
nodes; Mextram has 4 internal collectors (c1, c2, c3, c4).
I'm not sure we should be recommending names, but I'm interested
to know what sorts of "better optimization" might be possible
if the names were consistent.

Certainly, one could see that "D" and "int_d" might be connected
with a resistance that could be shorted, thus collapsing "int_d"
But isn't this a property of the resistor, and we should work on
hints for collapsable resistors, rather than trying to make up
a list of all the "special" internal node names?

[Jushan Xie]

Hi Geoffrey,

The following is what I am thinking:

1. Verilog-A compact model should follow compact convention on port order definition, this is not a big deal. Designer will feel there is no difference between Verilog-A and simulator build-in model, there will be also less trouble for other EDA tools, like parasitic extraction that handle source/drain/gate differently, etc. Although Verilog-A allows arbitrary port order, it creates trouble if it doesn't follow compact model port order convention.

2. One issue of Verilog-A model is simulation performance. Optimization is needed whenever it is possible. Defining rules and guideline for compact Verilog-A model will help Verilog compiler optimization. It will be beneficial for user. It is highly recommend that Verilog-A compact model should define rules and guideline to improve Verilog-A performance.

Thanks,
Jushan