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CMC Verilog-A
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rdk
,
Geoffrey Coram
3
4/22/13
Use of arrays, per LRM 2.3.1
Hi, Richard - I don't have all the answers, but I have a few. > *Can an element of an array be
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Use of arrays, per LRM 2.3.1
Hi, Richard - I don't have all the answers, but I have a few. > *Can an element of an array be
4/22/13
Geoffrey Coram
9/21/12
Preliminary recommendations document
I'm attaching a document which contains some of the recommendations that have been discussed in
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Preliminary recommendations document
I'm attaching a document which contains some of the recommendations that have been discussed in
9/21/12
Geoffrey Coram
, …
Alfredo Piazza
33
12/27/11
restricting ddx()
"ddx terms that are contributing to current would have to be computed correctly even though the
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restricting ddx()
"ddx terms that are contributing to current would have to be computed correctly even though the
12/27/11
Geoffrey
, …
Geoffrey Coram
9
12/16/11
Parameter Declarations
The model author would need to put the backslash in -- if I had written BSIMSOI with the parameters
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Parameter Declarations
The model author would need to put the backslash in -- if I had written BSIMSOI with the parameters
12/16/11
Geoffrey Coram
2
12/13/11
module declaration attribute
What sorts of optimizations might this enable? What is the list of device types -- is it just generic
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module declaration attribute
What sorts of optimizations might this enable? What is the list of device types -- is it just generic
12/13/11
rdk
, …
Dan Fitzpatrick
17
11/3/11
implementation of @(initial_step)
Geoffrey, Then I guess I missed why this even came up as the situation for how to handle this is as
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implementation of @(initial_step)
Geoffrey, Then I guess I missed why this even came up as the situation for how to handle this is as
11/3/11
Geoffrey Coram
,
Jushan Xie
2
9/21/11
port and node name conventions
Hi Geoffrey, The following is what I am thinking: 1. Verilog-A compact model should follow compact
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port and node name conventions
Hi Geoffrey, The following is what I am thinking: 1. Verilog-A compact model should follow compact
9/21/11
Geoffrey
, …
Geoffrey Coram
10
9/16/11
Switch Branches
I certainly agree that using parameters/localparams would be easier from a compiler/simulator
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Switch Branches
I certainly agree that using parameters/localparams would be easier from a compiler/simulator
9/16/11
Geoffrey Coram
9/15/11
correlated noise
According to the Verilog-A LRM, one can do the following: real n; n = white_noise(pwr); V(a,b) <+
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correlated noise
According to the Verilog-A LRM, one can do the following: real n; n = white_noise(pwr); V(a,b) <+
9/15/11
Geoffrey Coram
8/16/11
CMC Verilog-A references
Greetings! This is the first message for the discussion group. Below are some references I'm
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CMC Verilog-A references
Greetings! This is the first message for the discussion group. Below are some references I'm
8/16/11
