Vitis and XRT not enabling on oct-build

[Prithviraj Yuvaraj]

Last login: Tue May 19 07:40:26 2026 from 172.248.185.167
-bash: /opt/xilinx/xrt/setup.sh: No such file or directory
-bash: /share/Xilinx/Vitis/2023.2/settings64.sh: No such file or directory
pyuvaraj@fpga-tools:~$ 

[Suranga Handagala]

Can you share the link to the experiment?

[Prithviraj Yuvaraj]

https://www.cloudlab.us/status.php?uuid=da6525dc-7163-4733-87d0-4d77f270edf3#

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[Handagala, Suranga]

We recently updated the file system for tools, so running which vitis should now point to: /fpga/Xilinx/Vitis/2023.2/bin/vitis

Regarding the XRT issue, are you seeing any errors in the installation log at /local/logs/output_log.txt?

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[Prithviraj Yuvaraj]

Hello I was able to resolve this issue by creating a new build server with the new profile. But I am having an issue building now:

make[1]: Entering directory '/users/pyuvaraj/SmallBank/build'
make[2]: Entering directory '/users/pyuvaraj/SmallBank/build'
make[3]: Entering directory '/users/pyuvaraj/SmallBank/build'
make[3]: Leaving directory '/users/pyuvaraj/SmallBank/build'
make[3]: Entering directory '/users/pyuvaraj/SmallBank/build'

****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2023.2 (64-bit)
  **** SW Build 4023990 on Oct 11 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source /fpga/Xilinx/Vitis_HLS/2023.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/fpga/Xilinx/Vitis_HLS/2023.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'pyuvaraj' on host 'fpga-build1vm-2.cloudlab.umass.edu' (Linux_x86_64 version 5.15.0-177-generic) on Wed May 20 15:10:40 MDT 2026
INFO: [HLS 200-10] On os Ubuntu 22.04.2 LTS
INFO: [HLS 200-10] In directory '/users/pyuvaraj/SmallBank/build/deposit_merger'
INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl
Sourcing Tcl script 'make.tcl'
INFO: [HLS 200-1510] Running: open_project deposit_merger_prj
INFO: [HLS 200-10] Opening project '/users/pyuvaraj/SmallBank/build/deposit_merger/deposit_merger_prj'.
INFO: [HLS 200-1510] Running: open_solution solution1
INFO: [HLS 200-10] Opening solution '/users/pyuvaraj/SmallBank/build/deposit_merger/deposit_merger_prj/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.333ns.
INFO: [HLS 200-1505] Using flow_target 'vivado'
Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html
INFO: [HLS 200-435] Setting 'open_solution -flow_target vivado' configuration: config_interface -m_axi_latency=0
INFO: [HLS 200-435] Setting 'open_solution -flow_target vivado' configuration: config_interface -m_axi_alignment_byte_size=1
INFO: [HLS 200-435] Setting 'open_solution -flow_target vivado' configuration: config_interface -m_axi_max_widen_bitwidth=0
INFO: [HLS 200-435] Setting 'open_solution -flow_target vivado' configuration: config_rtl -register_reset_num=0
INFO: [HLS 200-1464] Running solution command: config_interface -m_axi_latency=64
INFO: [HLS 200-1464] Running solution command: config_interface -m_axi_alignment_byte_size=64
INFO: [HLS 200-1464] Running solution command: config_interface -m_axi_max_widen_bitwidth=512
INFO: [HLS 200-1464] Running solution command: config_rtl -register_reset_num=3
INFO: [HLS 200-1464] Running solution command: config_export -format=xo
INFO: [HLS 200-1510] Running: set_part xcu280-fsvh2892-2L-e
ERROR: [HLS 200-1608] Failed to open platform database.
command 'ap_source' returned error code
    while executing
"source make.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $tclfile] "

INFO: [HLS 200-112] Total CPU user time: 1.37 seconds. Total CPU system time: 0.27 seconds. Total elapsed time: 1.8 seconds; peak allocated memory: 220.906 MB.
INFO: [Common 17-206] Exiting vitis_hls at Wed May 20 15:10:41 2026...
make[3]: *** [deposit_merger/CMakeFiles/synthesis.deposit_merger.dir/build.make:60: deposit_merger/CMakeFiles/synthesis.deposit_merger] Error 1
make[3]: Leaving directory '/users/pyuvaraj/SmallBank/build'
make[2]: *** [CMakeFiles/Makefile2:1879: deposit_merger/CMakeFiles/synthesis.deposit_merger.dir/all] Error 2
make[2]: Leaving directory '/users/pyuvaraj/SmallBank/build'
make[1]: *** [CMakeFiles/Makefile2:254: load/CMakeFiles/installip.dir/rule] Error 2
make[1]: Leaving directory '/users/pyuvaraj/SmallBank/build'
make: *** [Makefile:170: installip] Error 2

It seems that the part I am trying to set with the vitis_hls workflow the platform database can't open? This workflow would work on the previous profile. 

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[Suranga Handagala]

I reinstalled Vitis HLS 2023.2. Please try now.

[Prithviraj Yuvaraj]

So i remade an oct-build machine, and i get the same error.