Using a Signal as a Clock

[Anmol Sahoo]

Could someone give me a pointer as to how I could use a Signal as a Clock for another module? My main aim is to create custom clock frequencies, e.g. a Baud rate generator for UART. 

As far as I have read, the Clock type only has value constructors for Clock and GatedClock. Would I have to create a function which takes a type Signal and returns a Clock? The other option would be to manually maintain state inside the module and update the state based on the number of clock cycles that have ellapsed, to meet the required frequency. I'm not really sure how this would work out, thus would like some directions. 

[Anmol Sahoo]

Thank you. That is really helpful! :D

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Warm regards,

Anmol Sahoo

Project Associate | Dept. of CSE, IIT Madras

+91 9769504438

The views and opinions expressed in this mail are attributable only to Anmol Sahoo unless explicitly stated and cannot be construed to represent the position of any organization I am currently or previously attached with. 

On Wed, Aug 15, 2018 at 4:50 PM, Peter Lebbing <pe...@digitalbrains.com> wrote:

On 15/08/18 10:35, Anmol Sahoo wrote:
> The other option would be to manually
> maintain state inside the module and update the state based on the
> number of clock cycles that have ellapsed, to meet the required
> frequency. I'm not really sure how this would work out, thus would like
> some directions. 

This is what I wrote in CλaSH v0.3.3 (really ancient) to implement an
UART. Well, the clock scaling was for many more purposes as well. I
ported it to CλaSH v0.7, I don't have a version for v0.99 yet.

See the gist: [1]

To instantiate an UART, use, f.e.:

--8<---------------cut here---------------start------------->8---
        tTick = mealy $(CS.staticAvgRate fClk 115200) 1 sCmd
        (sCmd, txDone, txd) = Serial.output (tTick, txiV, txi)
        rTick = mealy $(CS.staticAvgRate fClk (16*115200)) 1 (pure CS.Run)
        (rxoF, rxoV) = Serial.input (rTick, rxd)
--8<---------------cut here---------------end--------------->8---

txd, rxd are the pins on the FPGA (add synchronization on rxd). txi byte
to send when txiV True. When rxoV is True, rxoF is received data (see
documentation).

HTH,

Peter.

[1] <https://gist.github.com/DigitalBrains1/f428e3edf5043723f8f3f0705e637a32>

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[Peter Lebbing]

Resend from the e-mail account that is actually subscribed to this
Google Group. Sorry for the mixup, Anmol.

On 15/08/18 10:35, Anmol Sahoo wrote:

> The other option would be to manually
> maintain state inside the module and update the state based on the
> number of clock cycles that have ellapsed, to meet the required
> frequency. I'm not really sure how this would work out, thus would like
> some directions. 

[Peter Lebbing]

On 15/08/18 13:23, Anmol Sahoo wrote:
> Thank you. That is really helpful! :D

Ah, that's good to hear!

It still missed the file Toolbox/Misc.hs, I overlooked the fact it was
used. I have added it to the gist now.

Peter.

[Anmol Sahoo]

Thank you for that. While this is really helpful, I would also like to know if there could be some way to coerce normal signals into clock signals, as then I could retain the type-safety of the Clock datatype. I'll try to figure out on my own as well, but if someone comes up with ideas, I'd be glad to hear! 

[Christiaan Baaij]

Using clash-0.99.* terminology: 

While it is not possible to convert `Signal domain Bool` to a `Clock domain 'Source` (nor will it ever be possible)

It is possible to disable/enable logic using by enabling/gating the clock using `clockGate` [1]:

clockGate :: Clock domain gated -> Signal domain Bool -> Clock domain 'Gated

[1] http://hackage.haskell.org/package/clash-prelude-0.99.3/docs/Clash-Explicit-Signal.html#v:clockGate

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[Anmol Sahoo]

Yeah. That makes sense. I will try and work with that. Thank you Mr. Baaij. Big fan of your work!

[Koen Raben]

Good morning,
Could someone maybe give me pointers how to implement this clockGate behaviour in a more recent version of Clash (currently using 1.4.6)? As far as I understand, the clockGate function as mentioned above does no longer exist. I am looking to disable the clock to parts of my design for power optimization purposes in an ASIC environment. Any help would be appreciated! 

Best regards,
Koen Raben  

[Christiaan Baaij]

It's my experience that the tools like it better when they get to infer clock gating from registers with enables, as opposed to manually inserting clock gating logic.

All register/delay functions have such an enable input:

- https://hackage.haskell.org/package/clash-prelude-1.4.6/docs/Clash-Explicit-Signal.html#v:delay

- https://hackage.haskell.org/package/clash-prelude-1.4.6/docs/Clash-Explicit-Signal.html#v:delayMaybe

- https://hackage.haskell.org/package/clash-prelude-1.4.6/docs/Clash-Explicit-Signal.html#v:delayEn

- https://hackage.haskell.org/package/clash-prelude-1.4.6/docs/Clash-Explicit-Signal.html#v:register

- https://hackage.haskell.org/package/clash-prelude-1.4.6/docs/Clash-Explicit-Signal.html#v:regMaybe

See 

- Section https://hackage.haskell.org/package/clash-prelude-1.4.6/docs/Clash-Explicit-Signal.html#g:6

and

- https://hackage.haskell.org/package/clash-prelude-1.4.6/docs/Clash-Explicit-Signal.html#v:enable   (renamed in 1.6.1 to https://hackage.haskell.org/package/clash-prelude-1.6.1/docs/Clash-Explicit-Signal.html#v:andEnable)

On how to control the Enable explicitly.

When you're working with hidden clocks/resets/enables check out

- https://hackage.haskell.org/package/clash-prelude-1.4.6/docs/Clash-Signal.html#v:withEnable

To hook up a specific enable signal

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[Koen Raben]

Hey Christiaan, 

Unfortunately the Synopsys tooling I am using tends to produce designs which do not function correctly if I let it insert clock gating. For that reason (and a bit for research purposes) I would like to implement it myself.
Is it possible to implement this through Clash?

Best regards,
Koen Raben

[Christiaan Baaij]

So Clash never actually implemented "true" clock gating.

Even in pre-1.0, a `Clock dom Gated` was actually a tuple of a clock line and an enable line.

And https://hackage.haskell.org/package/clash-prelude-0.99.3/docs/Clash-Explicit-Signal.html#v:clockGate just added an and-gate to that enable line.

You could create your own primitive, see

- https://hackage.haskell.org/package/clash-prelude-1.4.7/docs/Clash-Tutorial.html#g:14, and

- https://hackage.haskell.org/package/clash-prelude-1.4.7/docs/Clash-Annotations-Primitive.html#t:Primitive (check InlinePrimitive)

Where you instantiate one of clock gating IP from the Synopsys library (or build your own version of glitch-free clock gating logic)

And give it a Haskell type-signature of:

clockGate :: Clock dom -> Signal dom Bit -> Clock dom

clockGate (Clock name) _ = Clock name

{-# NOINLINE clockGate #-}

As you can see, it's not actually possible to then simulate the clock gating in Haskell/Clash, because the clock type doesn't actually carry this "gatedness" info.

We would have to change the Clock datatype to e.g.:

data Clock dom = Clock (SSymbol dom) (Signal dom Bool)

And then have all the existing memory primitives treat that 'Signal dom Bool' as another "enable".

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[Koen Raben]

I have implemented your suggestion of creating the primitive and it works!
Thank you very much for the help.

Best regards,
Koen Raben