Problems With Blinker Starter Project

[Pat the Builder]

Howsgoin,

Not sure where to post this as it's not a compiler issue.

There are some errors in the sources of the _blinker_ starter project on https://qbaylogic.com/all/clash/clash-fpga-starter.

• First there's an error in the html of the sources: please substitute @->@ for @->@;
• When I compile with @--vhdl@ I get the following error (I just refreshed @clash@ with @snap@: version 1.5.0):

    Blinker.lhs:90:7: error:
        * Couldn't match expected type `Enable dom0 -> Reset Dom20MHz'
                      with actual type `Reset Dom20MHz'
        * The function `resetSynchronizer' is applied to three arguments,
          but its type `Clock Dom20MHz -> Reset Dom20MHz -> Reset Dom20MHz'
          has only two
          In the expression:
            resetSynchronizer clk20Mhz (unsafeFromLowPolarity pllStable) en
          In an equation for `rstSync':
              rstSync
                = resetSynchronizer clk20Mhz (unsafeFromLowPolarity pllStable) en

FWIW Installing clash is now a delight. This used to take a lot of time but this time the installation went without any problems. I still have to sort out some problems which are caused by the new destination directories of the @vhdl@ files but that should be easy (fingers crossed)?

Regards/Wash hands/Wear face mask/etc,

Paddy

[Peter Lebbing]

Hello Paddy!

> Not sure where to post this as it's not a compiler issue.

Here seems fine to me.

> * First there's an error in the html of the sources: please substitute @->@ for @->@;

Interesting! Thanks for reporting this. The source is here:
https://github.com/QBayLogic/qbaymid/blob/master/source/posts/new-clash-fpga-starter.html.markdown.erb
Apparently we need to do something special to have the > survive.

> * When I compile with @--vhdl@ I get the following error (I just refreshed @clash@ with @snap@: version 1.5.0):

>     Blinker.lhs:90:7: error:
>         * Couldn't match expected type `Enable dom0 -> Reset Dom20MHz'
>                       with actual type `Reset Dom20MHz'
>         * The function `resetSynchronizer' is applied to three arguments,
>           but its type `Clock Dom20MHz -> Reset Dom20MHz -> Reset Dom20MHz'
>           has only two
>           In the expression:
>             resetSynchronizer clk20Mhz (unsafeFromLowPolarity pllStable) en
>           In an equation for `rstSync':
>               rstSync
>                 = resetSynchronizer clk20Mhz (unsafeFromLowPolarity pllStable) en

That's actually a difference between Clash 1.4 and current `master`
(a.k.a. 1.5.0):
https://github.com/clash-lang/clash-compiler/pull/1964

I think the website should correspond to the latest stable release, so
this is something to change once we release 1.6. Or maybe not change per
se, we had "CλaSH FPGA Starter" and then "New Clash FPGA Starter", so I
propose "New new Clash FPGA Starter" modulo spelling changes? ;-)

> FWIW Installing clash is now a delight. This used to take a lot of
> time but this time the installation went without any problems.

That's good to hear!

> I still have to sort out some problems which are caused by the new
> destination directories of the @vhdl@ files but that should be easy
> (fingers crossed)?

Good luck with all those little adjustments...

Regards and enjoy Christmas if that's something you do,

Peter.