First clock period in generated testbench shorter than designed clock period

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Koen Raben

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Nov 17, 2021, 4:40:54 AM11/17/21
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Hi,

When generating a verilog testbench and a clock signal with a period of 20 ns the first half-period of the clock is set to 3 ns instead of the expected 10 ns. I have included the relevant part of the verilog code below. What is the cause of this deviating clock period and how would I be able to change it from my Clash description?

Any help is greatly appreciated!

Kind Regards,
Koen Raben

Verilog snippet:
// tbClockGen begin
  // pragma translate_off
  reg  clk_0;
  // 1 = 0.1ps
  localparam half_period = (200000 / 2);
  always begin
    // Delay of 1 mitigates race conditions (https://github.com/steveicarus/iverilog/issues/160)
    #1 clk_0 =  0 ;
    #30000 forever begin //<------------- Where does this number come from?
      if (~ (~ c$result_rec)) begin
        $finish;
      end
      clk_0 = ~ clk_0;
      #half_period;
      clk_0 = ~ clk_0;
      #half_period;
    end
  end


Christiaan Baaij

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Nov 17, 2021, 5:28:25 AM11/17/21
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I define the period as the time between two active edges.
Looking at the generated code, it seems that you're using positive-edge triggered logic.
For a 20ns clock, The first active edge, going from 0 to 1, happens at 3.0001ns the second active edge happens at 23.0001ns, the third at 43.0001ns, etc.
So the period is definitely 20ns.

The 3ns was definitely picked arbitrarily.
But whether the first active edge happens at 0.0002ns (it must happen at time-step 2 (0.2ps) because of the mentioned race-condition avoidance) or at 3.0001ns doesn't really matter, no?

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Christiaan Baaij

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Nov 17, 2021, 6:04:12 AM11/17/21
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Is the time from simulation start until the first active edge being shorter than the period causing problems in a post-synthesis simulation?
If you have register models that checks stable values in the setup/hold window I can imagine that this would be a problem.

Koen Raben

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Nov 17, 2021, 6:08:46 AM11/17/21
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Hey Christiaan,

That is exactly the problem I ran into. In post-synthesis simulations the setup time is not long enough for all signals to become stable. 
I shall submit the issue.

Kind regards,
Koen Raben 
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