An issue in generating verilog file

[Farhad A]

Hello everyone,

I have an issue in generating verilog file from Clash compiler. It generates VHDL file properly with testbench, but after compiling all modules during Verilog generation, the weird error that I've attached here will pop up and verilog directory will be created with empty Verilog file. I would be appreciated if you could help me with this problem. Thanks in advance.

Cheers,

Farhad

[mar...@qbaylogic.com]

Hi Farhad,

I believe this might have been fixed in:

https://github.com/clash-lang/clash-compiler/commit/b48575b22b2ed37b96f31a004c5d707a1788f585

This fix is in master, but I'll backport it to Clash 1.4:

https://github.com/clash-lang/clash-compiler/pull/1886

I'll keep you posted.

Kind regards,

Martijn

Op zaterdag 31 juli 2021 om 08:24:15 UTC+2 schreef farhad...@gmail.com:

[Farhad A]

Hi Martijn,

Thanks for your response. Can you please explain how can I apply this fix? I installed Clash using snap store in Ubuntu. Do I need to just changes those additions and deletions mentioned in that post?

Regards,

Farhad

[mar...@qbaylogic.com]

Hi Farhad,

With the snap there's no good way of applying the patch. Typically you'd run Clash using Cabal/Stack as described in "Option B" over here: https://clash-lang.org/install/linux/. Both build systems allow you to pick an arbitrary git commit to build Clash from.

I'm going to try and release Clash v1.4.3 today though, which includes your fix. Either waiting or "snap refresh" should install the new version when it's released.

Martijn

Op zaterdag 31 juli 2021 om 17:59:16 UTC+2 schreef farhad...@gmail.com:

[Farhad A]

Hi Martjin,

Thanks for your help and explanation. I went through the Stack tutorial as you mentioned which fixed my issue. From now on, I will use this approach. Thanks again.

Best regards,

Farhad