Using -fclash-clear

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Pat the Builder

Dec 24, 2021, 8:27:56 PM12/24/21
to Clash - Hardware Description Language

I haven't used Clash for a long time and I am trying to adjust my workflow. I use Quartus as my vhdl compiler.

I'm getting some unexpected problem. I'll use the Blinker project to explain the problem. For some reason Clash now makes assumptions about the presence/ previous state of vhd sources in the vhdl/Blinker.topEntity directory. E.g. I removed all vhdl files from the directory and then ran

    clash  -fclash-no-cache --fdiagnostics-color=always -fclash-hdlsyn Quartus --vhdl Blinker.lhs

Notice that I used @-fclash-no-cache@ to convince Clash it shouldn't make any assumptions abuot previous Clash runs. To my surprise (?) I got

    Clash error call:
    Changes were made to vhdl/Blinker.topEntity after last Clash run:
      * Unexpected removed file blinker.vhdl
      * Unexpected removed file blinker_types.vhdl
      * Unexpected removed file resetSynchronizer.vhdl
      * Unexpected extra file Blinker.asm.rpt
      * and 18 more unexpected changes
    Use '-fclash-clear' if you want Clash to clear out the directory. Warning: this will
    remove the complete directory, be cautious of data loss.
    CallStack (from HasCallStack):
      error, called at src/Clash/Driver.hs:846:9 in clash-lib-1.4.6-2yAQB0iRvaGF0r2r9D5CFW:Clash.Driver

I assume Clash is trying to be clever and avoid unnecessary re-compilations?

All my Quartus project files are in the vhdl/Blinker.topEntity directory, so I must now figure out which Quartus project files are needed, save them, use @-fclash-clear@, move the project files back again. Clearly there are too many things which may go wrong in this process. (Also the Blinker project isn't my only project.)

Am I overlooking an easier solution?


Pat the Builder

Dec 25, 2021, 1:25:58 AM12/25/21
to Clash - Hardware Description Language
As it turned out, there were only two Quartus files which Clash didn't like. When I now generate VHDL with Clash and @-fclash-clear@, then restore the quartus files, generate a netlist with Quartus, and then execute the netlist on FPGA, everything is fine.
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