blockRam with two read ports for synthesis

[peter.t...@gmail.com]

Is there yet an approved way to put in a blockRam with TWO read ports and have it recognized by the synthesis backend for mapping to a standard FPGA component?

All FPGAs that I have asked about seem to have multiport RAM nowadays.

At the moment I am emulating two read ports on RAM by putting two blockRams in parallel, driving them both with the same write signal, and using the two read ports separately.

That wastes memory!

The answer is to write ones own backend primitive, but unfortunately I cannot make head or tail of the tutorial. I need to know what is wanted, and how to supply what that is (the latter may be in the tutorial, but the crucial "what is wanted" part is not).

Best regards

Peter

PS. FPGAs also have two write ports on RAM usually, but I can deal with that (merge two write signals into one and choose to do something at collisions).