[PATCH stable 5.4 04/11] crypto: arm/sha256-neon - avoid ADRL pseudo instruction

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Florian Fainelli

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Jun 29, 2022, 2:02:47 PM6/29/22
to sta...@vger.kernel.org, Ard Biesheuvel, Nick Desaulniers, Herbert Xu, Florian Fainelli, Russell King, David S. Miller, Tony Lindgren, Hans Ulli Kroll, Stefan Agner, Nicolas Pitre, Andre Przywara, Russell King (Oracle), Greg Kroah-Hartman, Catalin Marinas, Jian Cai, moderated list:ARM PORT, open list, open list:CRYPTO API, open list:OMAP2+ SUPPORT, open list:CLANG/LLVM BUILD SUPPORT, Sasha Levin
From: Ard Biesheuvel <ar...@kernel.org>

commit 54781938ec342cadbe2d76669ef8d3294d909974 upstream

The ADRL pseudo instruction is not an architectural construct, but a
convenience macro that was supported by the ARM proprietary assembler
and adopted by binutils GAS as well, but only when assembling in 32-bit
ARM mode. Therefore, it can only be used in assembler code that is known
to assemble in ARM mode only, but as it turns out, the Clang assembler
does not implement ADRL at all, and so it is better to get rid of it
entirely.

So replace the ADRL instruction with a ADR instruction that refers to
a nearer symbol, and apply the delta explicitly using an additional
instruction.

Signed-off-by: Ard Biesheuvel <ar...@kernel.org>
Tested-by: Nick Desaulniers <ndesau...@google.com>
Signed-off-by: Herbert Xu <her...@gondor.apana.org.au>
Signed-off-by: Florian Fainelli <f.fai...@gmail.com>
---
arch/arm/crypto/sha256-armv4.pl | 4 ++--
arch/arm/crypto/sha256-core.S_shipped | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/crypto/sha256-armv4.pl b/arch/arm/crypto/sha256-armv4.pl
index a03cf4dfb781..d927483985c2 100644
--- a/arch/arm/crypto/sha256-armv4.pl
+++ b/arch/arm/crypto/sha256-armv4.pl
@@ -175,7 +175,6 @@ $code=<<___;
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -471,7 +470,8 @@ sha256_block_data_order_neon:
stmdb sp!,{r4-r12,lr}

sub $H,sp,#16*4+16
- adrl $Ktbl,K256
+ adr $Ktbl,.Lsha256_block_data_order
+ sub $Ktbl,$Ktbl,#.Lsha256_block_data_order-K256
bic $H,$H,#15 @ align for 128-bit stores
mov $t2,sp
mov sp,$H @ alloca
diff --git a/arch/arm/crypto/sha256-core.S_shipped b/arch/arm/crypto/sha256-core.S_shipped
index 054aae0edfce..9deb515f3c9f 100644
--- a/arch/arm/crypto/sha256-core.S_shipped
+++ b/arch/arm/crypto/sha256-core.S_shipped
@@ -56,7 +56,6 @@
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -1885,7 +1884,8 @@ sha256_block_data_order_neon:
stmdb sp!,{r4-r12,lr}

sub r11,sp,#16*4+16
- adrl r14,K256
+ adr r14,.Lsha256_block_data_order
+ sub r14,r14,#.Lsha256_block_data_order-K256
bic r11,r11,#15 @ align for 128-bit stores
mov r12,sp
mov sp,r11 @ alloca
--
2.25.1

gre...@linuxfoundation.org

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Jun 30, 2022, 9:30:07 AM6/30/22
to andre.p...@arm.com, ar...@kernel.org, caij...@gmail.com, catalin...@arm.com, clang-bu...@googlegroups.com, da...@davemloft.net, f.fai...@gmail.com, gre...@linuxfoundation.org, her...@gondor.apana.org.au, linux-ar...@lists.infradead.org, li...@armlinux.org.uk, ndesau...@google.com, ni...@fluxnic.net, rmk+k...@armlinux.org.uk, sas...@kernel.org, ste...@agner.ch, to...@atomide.com, ulli....@googlemail.com, stable-...@vger.kernel.org

This is a note to let you know that I've just added the patch titled

crypto: arm/sha256-neon - avoid ADRL pseudo instruction

to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <sta...@vger.kernel.org> know about it.


From foo@baz Thu Jun 30 03:27:07 PM CEST 2022
From: Florian Fainelli <f.fai...@gmail.com>
Date: Wed, 29 Jun 2022 11:02:20 -0700
Subject: crypto: arm/sha256-neon - avoid ADRL pseudo instruction
To: sta...@vger.kernel.org
Cc: Ard Biesheuvel <ar...@kernel.org>, Nick Desaulniers <ndesau...@google.com>, Herbert Xu <her...@gondor.apana.org.au>, Florian Fainelli <f.fai...@gmail.com>, Russell King <li...@armlinux.org.uk>, "David S. Miller" <da...@davemloft.net>, Tony Lindgren <to...@atomide.com>, Hans Ulli Kroll <ulli....@googlemail.com>, Stefan Agner <ste...@agner.ch>, Nicolas Pitre <ni...@fluxnic.net>, Andre Przywara <andre.p...@arm.com>, "Russell King (Oracle)" <rmk+k...@armlinux.org.uk>, Greg Kroah-Hartman <gre...@linuxfoundation.org>, Catalin Marinas <catalin...@arm.com>, Jian Cai <caij...@gmail.com>, linux-ar...@lists.infradead.org (moderated list:ARM PORT), linux-...@vger.kernel.org (open list), linux-...@vger.kernel.org (open list:CRYPTO API), linux...@vger.kernel.org (open list:OMAP2+ SUPPORT), clang-bu...@googlegroups.com (open list:CLANG/LLVM BUILD SUPPORT), Sasha Levin <sas...@kernel.org>
Message-ID: <20220629180227.34...@gmail.com>

From: Ard Biesheuvel <ar...@kernel.org>

commit 54781938ec342cadbe2d76669ef8d3294d909974 upstream

The ADRL pseudo instruction is not an architectural construct, but a
convenience macro that was supported by the ARM proprietary assembler
and adopted by binutils GAS as well, but only when assembling in 32-bit
ARM mode. Therefore, it can only be used in assembler code that is known
to assemble in ARM mode only, but as it turns out, the Clang assembler
does not implement ADRL at all, and so it is better to get rid of it
entirely.

So replace the ADRL instruction with a ADR instruction that refers to
a nearer symbol, and apply the delta explicitly using an additional
instruction.

Signed-off-by: Ard Biesheuvel <ar...@kernel.org>
Tested-by: Nick Desaulniers <ndesau...@google.com>
Signed-off-by: Herbert Xu <her...@gondor.apana.org.au>
Signed-off-by: Florian Fainelli <f.fai...@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
---
arch/arm/crypto/sha256-armv4.pl | 4 ++--
arch/arm/crypto/sha256-core.S_shipped | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)

--- a/arch/arm/crypto/sha256-armv4.pl
+++ b/arch/arm/crypto/sha256-armv4.pl
@@ -175,7 +175,6 @@ $code=<<___;
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -471,7 +470,8 @@ sha256_block_data_order_neon:
stmdb sp!,{r4-r12,lr}

sub $H,sp,#16*4+16
- adrl $Ktbl,K256
+ adr $Ktbl,.Lsha256_block_data_order
+ sub $Ktbl,$Ktbl,#.Lsha256_block_data_order-K256
bic $H,$H,#15 @ align for 128-bit stores
mov $t2,sp
mov sp,$H @ alloca
--- a/arch/arm/crypto/sha256-core.S_shipped
+++ b/arch/arm/crypto/sha256-core.S_shipped
@@ -56,7 +56,6 @@
#else
.syntax unified
# ifdef __thumb2__
-# define adrl adr
.thumb
# else
.code 32
@@ -1885,7 +1884,8 @@ sha256_block_data_order_neon:
stmdb sp!,{r4-r12,lr}

sub r11,sp,#16*4+16
- adrl r14,K256
+ adr r14,.Lsha256_block_data_order
+ sub r14,r14,#.Lsha256_block_data_order-K256
bic r11,r11,#15 @ align for 128-bit stores
mov r12,sp
mov sp,r11 @ alloca


Patches currently in stable-queue which might be from f.fai...@gmail.com are

queue-5.4/arm-8971-1-replace-the-sole-use-of-a-symbol-with-its-definition.patch
queue-5.4/arm-omap2-drop-unnecessary-adrl.patch
queue-5.4/arm-8933-1-replace-sun-solaris-style-flag-on-section-directive.patch
queue-5.4/crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch
queue-5.4/arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-assembler.patch
queue-5.4/net-mscc-ocelot-allow-unregistered-ip-multicast-flooding.patch
queue-5.4/crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch
queue-5.4/arm-8989-1-use-.fpu-assembler-directives-instead-of-assembler-arguments.patch
queue-5.4/crypto-arm-ghash-ce-define-fpu-before-fpu-registers-are-referenced.patch
queue-5.4/arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-operand.patch
queue-5.4/crypto-arm-use-kconfig-based-compiler-checks-for-crypto-opcodes.patch
queue-5.4/arm-8990-1-use-vfp-assembler-mnemonics-in-register-load-store-macros.patch
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