Chao ca nha,
Co cai nay hay hay, ban nao quan tam thi tham gia nhe.
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Nguyen Thanh, Ph.D. Student
Dept. of Electrical and Electronic Eng.,
School of Electrical and Computer Eng.,
National Defense Academy
1-10-20 Hashirimizu, Yokosuka,
Kanagawa 239-8686, JAPAN
TEL: +81-468-41-3810 ext.3354
FAX: +81-468-44-5903
e-mail: ed1...@nda.ac.jp
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--- On Tue, 8/2/11, Darence Tan <Daren...@synopsys.com> wrote:
From: Darence Tan <Daren...@synopsys.com>
Subject: Invitation to Synopsys Seminar - IC Design Solutions Seminar, HCM Vietnam on 25 Aug 2011
To:
Date: Tuesday, August 2, 2011, 6:19 PM
Hi everyone, Synopsys will be conducting our very 1st IC Design solutions seminar in Sheraton Saigon on 25th Aug. This is a 1-Day FREE event. See below for the event details. Do sign-up and secure your place now as seats are limited. We already have more than 50 sign-up as of today. Register today so as to avoid disappointment…!! https://events.synopsys.com/sap(bD1lbiZjPTkxMA==)/bc/bsp/sap/zeventreg_ext/main.do?view_type=AUTH_VALIDATE BTW, we are giving away a iPAD2 in the lucky draw. Do remember to bring your name-card to enter the draw…. J Do forward this invitation to your colleagues or friends who may be interested to be part of this fast moving IC Design event…. J See you, Darence Tan Regional Sales Mgr South-East Asia Email: dar...@synopsys.com Direct: +65-6393-7111 Mobile: +65-9781-9802 
| Updated Registration Link
Our prior email inviting you to the IC Design Solutions Seminar contained an error in the registration link. We appologize for any
inconvienence and hope you will attend our seminar at the Sheraton Saigon Hotel & Towers, on August 25. |
IC Design Solutions Seminar
25 August, 2011 08.00 a.m. – 05.15 p.m. Sheraton Saigon Hotel & Towers 88 Dong Khoi Street, District 1 Ho Chi Minh City, Vietnam Level 3, Ballroom 3 Tel: (84)(8)38272828 You are cordially invited to attend the IC Design Solutions seminar presented by Synopsys technical experts. If you are an IC design or verification engineer or manager who wants to learn new techniques to improve productivity and predictability, this is a can’t-miss event! Overview This technical seminar provides a forum for IC design and verification engineers to learn about the latest Galaxy Implementation Platform, FPGA implementation, analog flow, and verification technologies and methodologies.
Learn about new capabilities and how to utilize them effectively to increase design implementation productivity and achieve performance, power, area and manufacturability goals for predictable silicon success. |
Agenda 08.00 – 08.50 a.m. Registration and Light Breakfast
08.50 – 09.00 a.m. Seminar Overview
09.00 – 09.45 a.m. Keynote: Mr. Don Chan, VP, Research & Development, Synopsys Inc. USA
09.45 – 10.15 a.m. Guest Speaker: Mr. Duytan Tran, VP, IP Engineering & Services, eSilicon, Vietnam.
10.15 – 10.45 a.m. Break
10.45 – 11.45 a.m. Front-end IC Design Flow: RTL Verification
11.45 – 12.30 p.m. FPGA Implementation Flow
12.30 – 02.00 p.m. Lunch
02.00 – 02.30 p.m. Guest Speaker: Mr. Cang Tran, VP, Renesas, Vietnam.
02.30 – 03.30 p.m. Back-end IC Design Flow:
Implementation Platform
03.30 – 04.00 p.m. Break
04.00 – 05.00 p.m. Analog IC Design Flow
05.00 – 05.15 p.m. Lucky Draw/Close |
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