[PATCH v2 0/2] clk: add assigned-clock-rates-u64

[Peng Fan (OSS)]

i.MX95 PLL VCO supports rates that exceeds UINT32_MAX, and the
i.MX95 System Controller Management Firmware(SCMI) server exports
PLL VCO for SCMI Agents to configure. So introduce
assigned-clock-rates-u64 to support rates that exceeds UINT32_MAX.
And introduce of_property_for_each_u64 to iterate each u64 rate.

The PR to add assigned-clock-rates-u64 to dt-schema has been merged:
https://github.com/devicetree-org/dt-schema/pull/140

Signed-off-by: Peng Fan <peng...@nxp.com>
---
Changes in v2:
- Follow what Luca did to of_property_for_each_u32 to write of_property_for_each_u64
- Link to v1: https://lore.kernel.org/r/20240621-clk-u64-...@nxp.com

---
Peng Fan (2):
of: property: add of_property_for_each_u64
clk: clk-conf: support assigned-clock-rates-u64

drivers/clk/clk-conf.c | 104 ++++++++++++++++++++++++++++++++++---------------
drivers/of/property.c | 23 +++++++++++
include/linux/of.h | 23 +++++++++++
3 files changed, 119 insertions(+), 31 deletions(-)
---
base-commit: 668d33c9ff922c4590c58754ab064aaf53c387dd
change-id: 20240621-clk-u64-70c4333f0f80

Best regards,
--
Peng Fan <peng...@nxp.com>

[Peng Fan (OSS)]

From: Peng Fan <peng...@nxp.com>

i.MX95 System Management Control Firmware(SCMI) manages the clock
function, it exposes PLL VCO which could support up to 5GHz rate that
exceeds UINT32_MAX. So add assigned-clock-rates-u64 support
to set rate that exceeds UINT32_MAX.

Signed-off-by: Peng Fan <peng...@nxp.com>
---

drivers/clk/clk-conf.c | 104 ++++++++++++++++++++++++++++++++++---------------
1 file changed, 73 insertions(+), 31 deletions(-)

diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index 058420562020..37b72600b296 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -78,47 +78,89 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)
return rc;
}

-static int __set_clk_rates(struct device_node *node, bool clk_supplier)
+static int __set_clk_rate(struct device_node *node, bool clk_supplier, int index,
+ unsigned long rate)
{
struct of_phandle_args clkspec;
- int rc, index = 0;
struct clk *clk;
- u32 rate;
+ int rc;

- of_property_for_each_u32(node, "assigned-clock-rates", rate) {
- if (rate) {
- rc = of_parse_phandle_with_args(node, "assigned-clocks",
+ rc = of_parse_phandle_with_args(node, "assigned-clocks",
"#clock-cells", index, &clkspec);
- if (rc < 0) {
- /* skip empty (null) phandles */
- if (rc == -ENOENT)
- continue;
- else
- return rc;
- }
- if (clkspec.np == node && !clk_supplier) {
- of_node_put(clkspec.np);
- return 0;
- }
+ if (rc < 0)
+ return rc;

- clk = of_clk_get_from_provider(&clkspec);
- of_node_put(clkspec.np);
- if (IS_ERR(clk)) {
- if (PTR_ERR(clk) != -EPROBE_DEFER)
- pr_warn("clk: couldn't get clock %d for %pOF\n",
- index, node);
- return PTR_ERR(clk);
+ if (clkspec.np == node && !clk_supplier) {
+ of_node_put(clkspec.np);
+ return 1;
+ }
+
+ clk = of_clk_get_from_provider(&clkspec);
+ of_node_put(clkspec.np);
+ if (IS_ERR(clk)) {
+ if (PTR_ERR(clk) != -EPROBE_DEFER)
+ pr_warn("clk: couldn't get clock %d for %pOF\n",
+ index, node);
+ return PTR_ERR(clk);
+ }
+
+ rc = clk_set_rate(clk, rate);
+ if (rc < 0)
+ pr_err("clk: couldn't set %s clk rate to %lu (%d), current rate: %lu\n",
+ __clk_get_name(clk), rate, rc, clk_get_rate(clk));
+ clk_put(clk);
+
+ return 0;
+}
+
+static int __set_clk_rates(struct device_node *node, bool clk_supplier)
+{
+ int rc, index = 0;
+ u64 rate;
+ u32 rate_32;
+ bool is_rate_32 = false;
+
+ if (!of_find_property(node, "assigned-clock-rates-u64", NULL))
+ is_rate_32 = true;
+
+ if (is_rate_32) {
+ of_property_for_each_u32(node, "assigned-clock-rates", rate_32) {
+ if (rate_32) {
+ rc = __set_clk_rate(node, clk_supplier, index, rate_32);
+
+ if (rc == 1 && !clk_supplier)
+ return 0;
+
+ if (rc < 0) {
+ /* skip empty (null) phandles */
+ if (rc == -ENOENT)
+ continue;
+ else
+ return rc;
+ }
}
+ index++;
+ }
+ } else {
+ of_property_for_each_u64(node, "assigned-clock-rates-u64", rate) {
+ if (rate) {
+ rc = __set_clk_rate(node, clk_supplier, index, rate);

- rc = clk_set_rate(clk, rate);
- if (rc < 0)
- pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n",
- __clk_get_name(clk), rate, rc,
- clk_get_rate(clk));
- clk_put(clk);
+ if (rc == 1 && !clk_supplier)
+ return 0;
+
+ if (rc < 0) {
+ /* skip empty (null) phandles */
+ if (rc == -ENOENT)
+ continue;
+ else
+ return rc;
+ }
+ }
+ index++;
}
- index++;
}
+
return 0;
}


--
2.37.1

[Peng Fan (OSS)]

i.MX95 PLL VCO supports rates that exceeds UINT32_MAX, and the
i.MX95 System Controller Management Firmware(SCMI) server exports
PLL VCO for SCMI Agents to configure. So introduce
assigned-clock-rates-u64 to support rates that exceeds UINT32_MAX.
And introduce of_property_for_each_u64 to iterate each u64 rate.

The PR to add assigned-clock-rates-u64 to dt-schema has been merged:
https://github.com/devicetree-org/dt-schema/pull/140

Signed-off-by: Peng Fan <peng...@nxp.com>
---

Changes in v3:
- Add R-b for patch 1
- Rewrite patch 2 to avoid duplicated code. Patch 2 not use code from
patch 1 now, but since patch 1 is a helper, so keep it.
- Link to v2: https://lore.kernel.org/r/20240729-clk-u64-...@nxp.com

Changes in v2:
- Follow what Luca did to of_property_for_each_u32 to write of_property_for_each_u64
- Link to v1: https://lore.kernel.org/r/20240621-clk-u64-...@nxp.com

---
Peng Fan (2):
of: property: add of_property_for_each_u64
clk: clk-conf: support assigned-clock-rates-u64

drivers/clk/clk-conf.c | 42 +++++++++++++++++++++++++++++++++++++-----
drivers/of/property.c | 23 +++++++++++++++++++++++
include/linux/of.h | 23 +++++++++++++++++++++++
3 files changed, 83 insertions(+), 5 deletions(-)
---
base-commit: 233a3e45c39db1e52061f3b6bbab9c630845dfad

[Peng Fan (OSS)]

From: Peng Fan <peng...@nxp.com>

i.MX95 System Management Control Firmware(SCMI) manages the clock
function, it exposes PLL VCO which could support up to 5GHz rate that
exceeds UINT32_MAX. So add assigned-clock-rates-u64 support
to set rate that exceeds UINT32_MAX.

Signed-off-by: Peng Fan <peng...@nxp.com>
---

drivers/clk/clk-conf.c | 42 +++++++++++++++++++++++++++++++++++++-----
1 file changed, 37 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index 058420562020..684e0c0738b3 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -81,11 +81,44 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier)

static int __set_clk_rates(struct device_node *node, bool clk_supplier)

{
struct of_phandle_args clkspec;
- int rc, index = 0;

+ int rc, count, index;

struct clk *clk;
- u32 rate;

+ u32 *rates __free(kfree);
+ bool rate_64 = false;
+
+ count = of_property_count_u64_elems(node, "assigned-clock-rates-u64");
+ if (count <= 0) {
+ count = of_property_count_u32_elems(node, "assigned-clock-rates");
+ if (count <= 0)
+ return 0;
+
+ rates = kcalloc(count, sizeof(u32), GFP_KERNEL);
+ if (!rates)
+ return -ENOMEM;
+ rc = of_property_read_variable_u32_array(node,
+ "assigned-clock-rates",
+ rates,
+ 1, count);
+ } else {
+ rates = kcalloc(count, sizeof(u64), GFP_KERNEL);
+ if (!rates)
+ return -ENOMEM;
+ rc = of_property_read_variable_u64_array(node,
+ "assigned-clock-rates-u64",
+ (u64 *)rates,
+ 1, count);
+ rate_64 = true;
+ }
+
+
+ for (index = 0; index < count; index++) {
+ unsigned long rate;
+
+ if (rate_64)
+ rate = ((u64 *)rates)[index];
+ else
+ rate = rates[index];

- of_property_for_each_u32(node, "assigned-clock-rates", rate) {

if (rate) {

rc = of_parse_phandle_with_args(node, "assigned-clocks",
"#clock-cells", index, &clkspec);

@@ -112,12 +145,11 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier)

rc = clk_set_rate(clk, rate);

if (rc < 0)
- pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n",

+ pr_err("clk: couldn't set %s clk rate to %lu (%d), current rate: %lu\n",

__clk_get_name(clk), rate, rc,
clk_get_rate(clk));
clk_put(clk);
}
- index++;
}
return 0;
}

--
2.37.1