[PATCH v4 0/4] net: stmmac: dwc-qos: Add FSD EQoS support

[Swathi K S]

SD platform has two instances of EQoS IP, one is in FSYS0 block and
another one is in PERIC block. This patch series add required DT binding,
DT file modifications and platform driver specific changes for the same.

Changes since v3:
1. Avoided using alias-id to configure the HW.
2. Addressed the review cooments on DT files given by Krzysztof
3. Modified the clock implementation.

Here is the link to v3 patches for reference:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230814112539.70...@samsung.com/
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230814112539.70...@samsung.com/
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230814112539.70...@samsung.com/
https://patchwork.kernel.org/project/linux-arm-kernel/patch/20230814112539.70...@samsung.com/

Swathi K S (4):
dt-bindings: net: Add FSD EQoS device tree bindings
net: stmmac: dwc-qos: Add FSD EQoS support
arm64: dts: fsd: Add Ethernet support for FSYS0 Block of FSD SoC
arm64: dts: fsd: Add Ethernet support for PERIC Block of FSD SoC

.../devicetree/bindings/net/snps,dwmac.yaml | 5 +-
.../devicetree/bindings/net/tesla,ethqos.yaml | 91 ++++++++++++++
arch/arm64/boot/dts/tesla/fsd-evb.dts | 18 +++
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 112 ++++++++++++++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 47 ++++++++
.../stmicro/stmmac/dwmac-dwc-qos-eth.c | 90 ++++++++++++++
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 28 ++++-
include/linux/stmmac.h | 1 +
8 files changed, 388 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/tesla,ethqos.yaml

--
2.17.1

[Swathi K S]

The FSD SoC contains two instance of the Synopsys DWC ethernet QOS IP core.
The binding that it uses is slightly different from existing ones because
of the integration (clocks, resets).

For FSD SoC, a mux switch is needed between internal and external clocks.
By default after reset internal clock is used but for receiving packets
properly, external clock is needed. Mux switch to external clock happens
only when the external clock is present.

Signed-off-by: Chandrasekar R <rcs...@samsung.com>
Signed-off-by: Suresh Siddha <ssi...@tesla.com>
Signed-off-by: Swathi K S <swat...@samsung.com>
---
.../stmicro/stmmac/dwmac-dwc-qos-eth.c | 90 +++++++++++++++++++
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 28 +++++-
include/linux/stmmac.h | 1 +
3 files changed, 117 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
index ec924c6c76c6..bc97b3b573b7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
@@ -20,6 +20,7 @@
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/stmmac.h>
+#include <linux/regmap.h>

#include "stmmac_platform.h"
#include "dwmac4.h"
@@ -37,6 +38,13 @@ struct tegra_eqos {
struct gpio_desc *reset;
};

+struct fsd_eqos_plat_data {
+ const struct fsd_eqos_variant *fsd_eqos_inst_var;
+ struct clk_bulk_data *clks;
+ int num_clks;
+ struct device *dev;
+};
+
static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
struct plat_stmmacenet_data *plat_dat)
{
@@ -265,6 +273,82 @@ static int tegra_eqos_init(struct platform_device *pdev, void *priv)
return 0;
}

+static int dwc_eqos_rxmux_setup(void *priv, bool external)
+{
+ int i = 0;
+ struct fsd_eqos_plat_data *plat = priv;
+ struct clk *rx1 = NULL;
+ struct clk *rx2 = NULL;
+ struct clk *rx3 = NULL;
+
+ for (i = 0; i < plat->num_clks; i++) {
+ if (strcmp(plat->clks[i].id, "eqos_rxclk_mux") == 0)
+ rx1 = plat->clks[i].clk;
+ else if (strcmp(plat->clks[i].id, "eqos_phyrxclk") == 0)
+ rx2 = plat->clks[i].clk;
+ else if (strcmp(plat->clks[i].id, "dout_peric_rgmii_clk") == 0)
+ rx3 = plat->clks[i].clk;
+ }
+
+ /* doesn't support RX clock mux */
+ if (!rx1)
+ return 0;
+
+ if (external)
+ return clk_set_parent(rx1, rx2);
+ else
+ return clk_set_parent(rx1, rx3);
+}
+
+static int fsd_clks_endisable(void *priv, bool enabled)
+{
+ struct fsd_eqos_plat_data *plat = priv;
+
+ if (enabled) {
+ return clk_bulk_prepare_enable(plat->num_clks, plat->clks);
+ } else {
+ clk_bulk_disable_unprepare(plat->num_clks, plat->clks);
+ return 0;
+ }
+}
+
+static int fsd_eqos_probe(struct platform_device *pdev,
+ struct plat_stmmacenet_data *data,
+ struct stmmac_resources *res)
+{
+ struct fsd_eqos_plat_data *priv_plat;
+ int ret = 0;
+
+ priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL);
+ if (!priv_plat)
+ return -ENOMEM;
+
+ priv_plat->dev = &pdev->dev;
+
+ ret = devm_clk_bulk_get_all(&pdev->dev, &priv_plat->clks);
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret, "No clocks available\n");
+
+ priv_plat->num_clks = ret;
+
+ data->bsp_priv = priv_plat;
+ data->clks_config = fsd_clks_endisable;
+ data->rxmux_setup = dwc_eqos_rxmux_setup;
+
+ ret = fsd_clks_endisable(priv_plat, true);
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "Unable to enable fsd clock\n");
+
+ return 0;
+}
+
+static void fsd_eqos_remove(struct platform_device *pdev)
+{
+ struct fsd_eqos_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev);
+
+ fsd_clks_endisable(priv_plat, false);
+}
+
static int tegra_eqos_probe(struct platform_device *pdev,
struct plat_stmmacenet_data *data,
struct stmmac_resources *res)
@@ -411,6 +495,11 @@ static const struct dwc_eth_dwmac_data tegra_eqos_data = {
.remove = tegra_eqos_remove,
};

+static const struct dwc_eth_dwmac_data fsd_eqos_data = {
+ .probe = fsd_eqos_probe,
+ .remove = fsd_eqos_remove,
+};
+
static int dwc_eth_dwmac_probe(struct platform_device *pdev)
{
const struct dwc_eth_dwmac_data *data;
@@ -473,6 +562,7 @@ static void dwc_eth_dwmac_remove(struct platform_device *pdev)
static const struct of_device_id dwc_eth_dwmac_match[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
{ .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data },
+ { .compatible = "tesla,fsd-ethqos", .data = &fsd_eqos_data },
{ }
};
MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 12689774d755..2ef82edec522 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -4001,6 +4001,12 @@ static int __stmmac_open(struct net_device *dev,
netif_tx_start_all_queues(priv->dev);
stmmac_enable_all_dma_irq(priv);

+ if (priv->plat->rxmux_setup) {
+ ret = priv->plat->rxmux_setup(priv->plat->bsp_priv, true);
+ if (ret)
+ netdev_err(priv->dev, "Rxmux setup failed\n");
+ }
+
return 0;

irq_error:
@@ -4056,7 +4062,13 @@ static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
static int stmmac_release(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
- u32 chan;
+ u32 chan, ret;
+
+ if (priv->plat->rxmux_setup) {
+ ret = priv->plat->rxmux_setup(priv->plat->bsp_priv, false);
+ if (ret)
+ netdev_err(priv->dev, "Rxmux setup failed\n");
+ }

if (device_may_wakeup(priv->device))
phylink_speed_down(priv->phylink, false);
@@ -7848,11 +7860,17 @@ int stmmac_suspend(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct stmmac_priv *priv = netdev_priv(ndev);
- u32 chan;
+ u32 chan, ret;

if (!ndev || !netif_running(ndev))
return 0;

+ if (priv->plat->rxmux_setup) {
+ ret = priv->plat->rxmux_setup(priv->plat->bsp_priv, false);
+ if (ret)
+ netdev_err(priv->dev, "Rxmux setup failed\n");
+ }
+
mutex_lock(&priv->lock);

netif_device_detach(ndev);
@@ -8018,6 +8036,12 @@ int stmmac_resume(struct device *dev)
mutex_unlock(&priv->lock);
rtnl_unlock();

+ if (priv->plat->rxmux_setup) {
+ ret = priv->plat->rxmux_setup(priv->plat->bsp_priv, true);
+ if (ret)
+ netdev_err(priv->dev, "Rxmux setup failed\n");
+ }
+
netif_device_attach(ndev);

return 0;
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 84e13bd5df28..f017b818d421 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -264,6 +264,7 @@ struct plat_stmmacenet_data {
void (*ptp_clk_freq_config)(struct stmmac_priv *priv);
int (*init)(struct platform_device *pdev, void *priv);
void (*exit)(struct platform_device *pdev, void *priv);
+ int (*rxmux_setup)(void *priv, bool external);
struct mac_device_info *(*setup)(void *priv);
int (*clks_config)(void *priv, bool enabled);
int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
--
2.17.1

[Swathi K S]

The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one
in FSYS0 block and other in PERIC block.

Adds device tree node for Ethernet in FSYS0 Block and enables the same for
FSD platform.

Signed-off-by: Pankaj Dubey <pankaj...@samsung.com>
Signed-off-by: Jayati Sahu <jayat...@samsung.com>

Signed-off-by: Swathi K S <swat...@samsung.com>
---

arch/arm64/boot/dts/tesla/fsd-evb.dts | 9 ++++
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 56 ++++++++++++++++++++++
arch/arm64/boot/dts/tesla/fsd.dtsi | 20 ++++++++
3 files changed, 85 insertions(+)

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 8d7794642900..2c37097c709a 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -64,6 +64,15 @@
};
};

+&ethernet_0 {
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
&fin_pll {
clock-frequency = <24000000>;
};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
index 3f898cf4874c..cb437483ff6e 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -64,6 +64,62 @@
samsung,pin-pud = <FSD_PIN_PULL_UP>;
samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
+
+ eth0_tx_clk: eth0-tx-clk-pins {
+ samsung,pins = "gpf0-0";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth0_tx_data: eth0-tx-data-pins {
+ samsung,pins = "gpf0-1", "gpf0-2", "gpf0-3", "gpf0-4";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth0_tx_ctrl: eth0-tx-ctrl-pins {
+ samsung,pins = "gpf0-5";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth0_phy_intr: eth0-phy-intr-pins {
+ samsung,pins = "gpf0-6";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_NONE>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ eth0_rx_clk: eth0-rx-clk-pins {
+ samsung,pins = "gpf1-0";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth0_rx_data: eth0-rx-data-pins {
+ samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth0_rx_ctrl: eth0-rx-ctrl-pins {
+ samsung,pins = "gpf1-5";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+
+ eth0_mdio: eth0-mdio-pins {
+ samsung,pins = "gpf1-6", "gpf1-7";
+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_NONE>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
};

&pinctrl_peric {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index 690b4ed9c29b..cc67930ebf78 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -1007,6 +1007,26 @@
clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
clock-names = "ref_clk";
};
+
+ ethernet_0: ethernet@15300000 {
+ compatible = "tesla,fsd-ethqos";
+ reg = <0x0 0x15300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I>,
+ <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I>,
+ <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I>,
+ <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I>,
+ <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I>;
+ clock-names = "ptp_ref", "master_bus", "slave_bus", "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth0_tx_clk>, <&eth0_tx_data>, <&eth0_tx_ctrl>,
+ <&eth0_phy_intr>, <&eth0_rx_clk>, <&eth0_rx_data>,
+ <&eth0_rx_ctrl>, <&eth0_mdio>;
+ local-mac-address = [00 00 00 00 00 00];
+ iommus = <&smmu_fsys0 0x0 0x1>;
+ phy-mode = "rgmii-id";
+ status = "disabled";
+ };
};
};

--
2.17.1

[Swathi K S]

Add FSD Ethernet compatible in Synopsys dt-bindings document. Add FSD
Ethernet YAML schema to enable the DT validation.

Signed-off-by: Pankaj Dubey <pankaj...@samsung.com>
Signed-off-by: Ravi Patel <ravi....@samsung.com>

Signed-off-by: Swathi K S <swat...@samsung.com>
---

.../devicetree/bindings/net/snps,dwmac.yaml | 5 +-
.../devicetree/bindings/net/tesla,ethqos.yaml | 91 +++++++++++++++++++
2 files changed, 94 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/tesla,ethqos.yaml

diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 3eb65e63fdae..0da11fe98cec 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -98,6 +98,7 @@ properties:
- snps,dwxgmac-2.10
- starfive,jh7100-dwmac
- starfive,jh7110-dwmac
+ - tesla,fsd-ethqos

reg:
minItems: 1
@@ -121,7 +122,7 @@ properties:

clocks:
minItems: 1
- maxItems: 8
+ maxItems: 10
additionalItems: true
items:
- description: GMAC main clock
@@ -133,7 +134,7 @@ properties:

clock-names:
minItems: 1
- maxItems: 8
+ maxItems: 10
additionalItems: true
contains:
enum:
diff --git a/Documentation/devicetree/bindings/net/tesla,ethqos.yaml b/Documentation/devicetree/bindings/net/tesla,ethqos.yaml
new file mode 100644
index 000000000000..9246b0395126
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/tesla,ethqos.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/tesla,ethqos.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: FSD Ethernet Quality of Service
+
+maintainers:
+ - Swathi K S <swat...@samsung.com>
+
+description:
+ dwmmac based tesla ethernet devices which support Gigabit
+ ethernet.
+
+allOf:
+ - $ref: snps,dwmac.yaml#
+
+properties:
+ compatible:
+ const: tesla,fsd-ethqos.yaml
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 5
+ maxItems: 10
+
+ clock-names:
+ minItems: 5
+ maxItems: 10
+
+ iommus:
+ maxItems: 1
+
+ phy-mode:
+ $ref: ethernet-controller.yaml#/properties/phy-connection-type
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - iommus
+ - phy-mode
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ethernet_1: ethernet@14300000 {
+ compatible = "tesla,fsd-ethqos";
+ reg = <0x0 0x14300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>,
+ <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>,
+ <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>,
+ <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
+ <&clock_peric PERIC_EQOS_PHYRXCLK>,
+ <&clock_peric PERIC_DOUT_RGMII_CLK>;

+ clock-names = "ptp_ref",

+ "master_bus",
+ "slave_bus",
+ "tx",
+ "rx",
+ "master2_bus",
+ "slave2_bus",
+ "eqos_rxclk_mux",
+ "eqos_phyrxclk",
+ "dout_peric_rgmii_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&eth1_tx_clk>, <&eth1_tx_data>, <&eth1_tx_ctrl>,
+ <&eth1_phy_intr>, <&eth1_rx_clk>, <&eth1_rx_data>,
+ <&eth1_rx_ctrl>, <&eth1_mdio>;
+ iommus = <&smmu_peric 0x0 0x1>;
+ phy-mode = "rgmii-id";
+ };
+
+...
--
2.17.1

[Swathi K S]

The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in
FSYS0 block and other in PERIC block.

Adds device tree node for Ethernet in PERIC Block and enables the same for
FSD platform.

Signed-off-by: Pankaj Dubey <pankaj...@samsung.com>
Signed-off-by: Jayati Sahu <jayat...@samsung.com>

Signed-off-by: Swathi K S <swat...@samsung.com>
---

arch/arm64/boot/dts/tesla/fsd-evb.dts | 9 ++++
arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 56 ++++++++++++++++++++++

arch/arm64/boot/dts/tesla/fsd.dtsi | 27 +++++++++++
3 files changed, 92 insertions(+)

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 2c37097c709a..80ca120b3d7f 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -73,6 +73,15 @@
};
};

+&ethernet_1 {

+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
&fin_pll {
clock-frequency = <24000000>;
};
diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi

index cb437483ff6e..6f4658f57453 100644
--- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi
@@ -437,6 +437,62 @@
samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
samsung,pin-drv = <FSD_PIN_DRV_LV4>;
};
+
+ eth1_tx_clk: eth1-tx-clk-pins {
+ samsung,pins = "gpf2-0";

+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_DOWN>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+

+ eth1_tx_data: eth1-tx-data-pins {
+ samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4";

+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+

+ eth1_tx_ctrl: eth1-tx-ctrl-pins {
+ samsung,pins = "gpf2-5";

+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+

+ eth1_phy_intr: eth1-phy-intr-pins {
+ samsung,pins = "gpf2-6";

+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;

+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
+
+ eth1_rx_clk: eth1-rx-clk-pins {
+ samsung,pins = "gpf3-0";

+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+

+ eth1_rx_data: eth1-rx-data-pins {
+ samsung,pins = "gpf3-1", "gpf3-2", "gpf3-3", "gpf3-4";

+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+

+ eth1_rx_ctrl: eth1-rx-ctrl-pins {
+ samsung,pins = "gpf3-5";

+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;
+ samsung,pin-drv = <FSD_PIN_DRV_LV6>;
+ };
+

+ eth1_mdio: eth1-mdio-pins {
+ samsung,pins = "gpf3-6", "gpf3-7";

+ samsung,pin-function = <FSD_PIN_FUNC_2>;
+ samsung,pin-pud = <FSD_PIN_PULL_UP>;

+ samsung,pin-drv = <FSD_PIN_DRV_LV4>;
+ };
};

&pinctrl_pmu {
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index cc67930ebf78..670f6a852542 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -1027,6 +1027,33 @@
phy-mode = "rgmii-id";
status = "disabled";
};

+
+ ethernet_1: ethernet@14300000 {
+ compatible = "tesla,fsd-ethqos";
+ reg = <0x0 0x14300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>,
+ <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>,
+ <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>,
+ <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>,
+ <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>,
+ <&clock_peric PERIC_EQOS_PHYRXCLK>,
+ <&clock_peric PERIC_DOUT_RGMII_CLK>;

+ clock-names = "ptp_ref", "master_bus", "slave_bus", "tx", "rx",
+ "master2_bus", "slave2_bus", "eqos_rxclk_mux",
+ "eqos_phyrxclk", "dout_peric_rgmii_clk";

+ pinctrl-names = "default";
+ pinctrl-0 = <&eth1_tx_clk>, <&eth1_tx_data>, <&eth1_tx_ctrl>,
+ <&eth1_phy_intr>, <&eth1_rx_clk>, <&eth1_rx_data>,
+ <&eth1_rx_ctrl>, <&eth1_mdio>;

+ local-mac-address = [00 00 00 00 00 00];

+ iommus = <&smmu_peric 0x0 0x1>;
+ phy-mode = "rgmii-id";