Software to get the devkit going
Volker Kuhlmann
sofware one will need to download to make use of the board, if it isn't
included on some disk with the kit? IIRC some packages were quite big. I
don't mind downloading 2GB but could get started on that now.
I was planning on picking up my board on Monday, but the forecast is
that not much might be taking place then and we might have to have an
e-meeting instead...
Thanks,
Volker
--
Volker Kuhlmann is list0570 with the domain in header.
http://volker.dnsalias.net/ Please do not CC list postings to me.
hamster
current (10 vs 11.0).
But that is good - it will match the howtos and examples that are on the
product CD.
Mike
Charles Manning
> Would someone who has opened the box already be able to tell what
> sofware one will need to download to make use of the board, if it isn't
> included on some disk with the kit? IIRC some packages were quite big. I
> don't mind downloading 2GB but could get started on that now.
Here's what I have found so far...
The kit comes with the V10.1 quartus (FPGA design) software for both Windows
and Linux. It does not seem to include the NIOS EDS which can be downloaded
from the Altera website. NB!!!! Make sure you download the correct version!
Alternately you can load the 11.0 stuff from Altera. Windows and Linux
versions avaliable. This includes the NIOS EDS so there is no need for
another download. These are large downloads.
I have 10.1 on Windows and 11.0 on Linux at present.
The kit also includes a DVD with the Terasic specific stuff including examples
etc.
The examples in the kit are geared to run on Windows, 10.1. I have not tried
them with other versions. The easy-run script is a *.bat file but I expect it
is easy enough to re-jig as a bash script.
-- Charles
Mark Atherton
hamster
Hi Mark,
Are you talking about multiple NIOS cores on the same Avalon bus, or
multiple completely independant processors?
Creating multiple independant processors should only be as hard as adding
multiple instances into the top level verilog file.
I've attempted to use the mid-range NIOS II/s (which has I and D caches)
but it appears to be licensed - tells me something about being time limited
when I try to flash. So at the moment I'm only able to create the "economy"
NIOS II/e, which only does 0.15 MIPS/MHz - the NIOS/s version is four times
faster, and the /f version twice that again. See
http://www.altera.com/literature/ds/ds_nios2_perf.pdf for performance
numbers.
Mike
Volker Kuhlmann
> The kit comes with the V10.1 quartus (FPGA design) software for both Windows
> and Linux. It does not seem to include the NIOS EDS which can be downloaded
> from the Altera website. NB!!!! Make sure you download the correct version!
OK thanks, that's only about 500MB for 10.1.
It would probably be useful to start with some examples from the devkit.
I'm not too worried about them being shown for MS-Windows, they should
run the same on Linux. Do they work equally well on the 11.0 edition
though?
One advantage of 11.0 seems to be the gcc 4.x toolchain (which Altera
recommends for all new designs) instead of the gcc 3.x one. That however
would only be useful if one was to make use of a CPU in the FPGA.
hamster
the project when you open it.
The actual contents of most of the demos is minimal. Once you get a demo
project running I found it very instructive to try and recreate the project
from scratch, just cutting and pasting the sources in. I learnt lots about
the DE0-nano system builder, Quartus II projects, pin mapping planning,
constraints, I/O standards, qsys, and so on tool.
I still can't believe how awesome Qsys/System Builder + Eclipse is:
- Select your components (processor, UART, memory...)
- Click with a mouse to join the wires and buses
- Define the system memory map
- Use Verilog in Quatus to wire the NIOS II to the outside world
- Compile and implement the design,
- Use the BSP builder to build the support library for your design
- Use Eclipse to write and compile your C application
- Download the hardware design to the FPGA
- Download the memory image to the NIOS II's memory
- Enjoy!
I still haven't worked out how to got something to simulate in Modelsim -
but I haven't needed to either.
One of the big challenges I see ahead for me is figuring out how to store
NIOS II code in the EPCS flash (along with the FPGA configuration), and
then using a boot loader stored in on-chip RAM to download that into the
external RAM, allowing the application code to persist across power cycles.
I'm hoping that it might just be something as easy as:
int main(int argc, char *argv[])
{
unsigned char *dram = 0x4000;
int (*myfunc)(int argc, char *arv[]);
/* Copy the code to DRAM */
for(i = 0; i < 0x10000; i++)
*dram[i] = EPCS_READ_BYTE(baseaddress+i);
/* now jump to the code in DRAM */
myfunc = (some stupid cast)dram;
return myfunc(argc, argv);
}
... but there is a whole lot of other stuff going on especially during the
linking of the code. Also the latency of the DRAM is far higher than the
on-chip RAM, so without the icache performance may be a lot lower. But if I
don't take advantage of the external RAM why bother?
In fact my new found love of NIOS II is fading fast, it might almost be a
one night stand - it seems you have to license the core it to get
- ICACHE
- DCACHE
- hardware multiply
- hardware divide
- MMU
- Performance greater than 15 MIPS
- Advanced hardware debugging
To me the NIOS II/e is starting to look more and more equivalent to
something like an 16MHz ATmega with a 32-bit registers. As the NIOS II's
instruction opcodes all 32 bits and both code and data share the same
memory resource it could be argued unless you have external DRAM the ATmega
will allow you to run bigger projects!
Mike.
On Mon, 15 Aug 2011 13:57:43 +1200, Volker Kuhlmann
<hid...@paradise.net.nz> wrote:
> It would probably be useful to start with some examples from the devkit.
> I'm not too worried about them being shown for MS-Windows, they should
> run the same on Linux. Do they work equally well on the 11.0 edition
> though?
>
> Volker
hamster
a look at this thread.
The third post has 'C' code that accesses the last block.
http://alterauserforum.com/forum/showthread.php?p=111306
Mike
Charles Manning
> On Mon 15 Aug 2011 09:55:05 NZST +1200, Charles Manning wrote:
>
>> The kit comes with the V10.1 quartus (FPGA design) software for both Windows
>> and Linux. It does not seem to include the NIOS EDS which can be downloaded
>> from the Altera website. NB!!!! Make sure you download the correct version!
>
> OK thanks, that's only about 500MB for 10.1.
>
> It would probably be useful to start with some examples from the devkit.
> I'm not too worried about them being shown for MS-Windows, they should
> run the same on Linux. Do they work equally well on the 11.0 edition
> though?
The examples seem to build fine under 11.0 too. They just give you a
warning that you are converting code from 10.1 to 11.
>
> One advantage of 11.0 seems to be the gcc 4.x toolchain (which Altera
> recommends for all new designs) instead of the gcc 3.x one. That however
> would only be useful if one was to make use of a CPU in the FPGA.
Yes, that gives you a more modern compiler which is probably better
supported into the future.
Charles Manning
>
> Hi Mark,
>
> Are you talking about multiple NIOS cores on the same Avalon bus, or
> multiple completely independant processors?
>
> Creating multiple independant processors should only be as hard as adding
> multiple instances into the top level verilog file.
>
> I've attempted to use the mid-range NIOS II/s (which has I and D caches)
> but it appears to be licensed - tells me something about being time limited
> when I try to flash. So at the moment I'm only able to create the "economy"
> NIOS II/e, which only does 0.15 MIPS/MHz - the NIOS/s version is four times
> faster, and the /f version twice that again. See
> http://www.altera.com/literature/ds/ds_nios2_perf.pdf for performance
> numbers.
>
> Mike
From what I have read, the /e version is unlimited but since it lacks
a cache it is going to be relatively slow if you're using SDRAM. It
might also lack a pipeline.
If you run the /e using internal RAM it would likely be faster than
running it with SDRAM.
The faster cores are nobbled under the free license to be runtime
limited to 1 hour or so or needing to be tethered.
Charles Manning
> All the demos I tried worked in 11.0sp1, It just prompts about upgrading
> the project when you open it.
>
> The actual contents of most of the demos is minimal. Once you get a demo
> project running I found it very instructive to try and recreate the project
> from scratch, just cutting and pasting the sources in. I learnt lots about
> the DE0-nano system builder, Quartus II projects, pin mapping planning,
> constraints, I/O standards, qsys, and so on tool.
Hamster, you're fast emerging as the guru. I hope you'll be able to
instruct us all at Volker's place.
From what I read you can still have those but they are either time
limited or tethered.
>
> To me the NIOS II/e is starting to look more and more equivalent to
> something like an 16MHz ATmega with a 32-bit registers. As the NIOS II's
> instruction opcodes all 32 bits and both code and data share the same
> memory resource it could be argued unless you have external DRAM the ATmega
> will allow you to run bigger projects!
I think you're right there.
I see the NIOSII/e as just a way to get a feel for softcores and the tools.
If you want to do something more hairy-chested then try a core from
opencores.org
Michael Field
> I hope you'll be able to instruct us all at Volker's place.
>
supposed to be today, but now delayed to tomorrow, and most likely will
be delayed again. Leaving her to look after the boy and a very saw mouth
is a bit unkind. :-)
Mike
hamster
I'm slowly working my way through the SDRAM datasheet. Is anybody
interested in using the SDRAM module outside of the "SOPC Builder"
environment? If so I'll through together a web page.... stuff like
Refresh requirements
---------------------
Refresh takes 7 cycles - one required at least every 770ns to achieve the
required 8192 refreshes every 64ms.
Command sequence
SYNC-NOP-NOP-NOP-NOP-NOP-NOP-<next command>
Read command
------------
Command Sequence for burst length of 2::
RAS-NOP-NOP-READ-NOP-PRE-NOP-NOP-<next command>
Data is valid two or three cycles after READ command depending on CAS.
Throughput
----------
* Numbers assume that a new row opened and closed for each burst
* No allowances for refresh (7 cycles every 770ns or about 9% of cycles at
100MHz)
Burst Length 1 word 2 words 4 words
100MHz CAS=2 28.6MB/s 50.0MB/s ...
100MHz CAS=3 33.2MB/s 57.2MB/s ...
Mike
Michael Field
It doesn't seem to be of much interest, but I've pretty much got enough
documentation on...
http://ec2-122-248-210-243.ap-southeast-1.compute.amazonaws.com/mediawiki/index.php/IS42S16160B-7
...to start working with the SDRAM.
I much prefer the M45W8MW16 Cellular RAM on my Nexys2...
Mike
hamster
If anybody wants to get up and running with their de0-nano, and can make
it to springston (just out from Lincoln) on Monday night, I'm on for a 7:30
till late FPGA hacking session...
Get the tools going, fire up uclinux, get a NIOS II built,get modelsim
going.... Whatever takes your fancy
Mike