Deduplication and unused outputs of modules

[Øyvind Harboe]

Deduplication doesn't take into account unused values.

So if I have module where an output is only used sometimes, then I don't get two verilog modules.

In the example below, is there a way to specify that I want unused outputs to be taken into account before de-duplication.

The motivation is to meet a requirement for no unused signals in a design prior to synthesis.

https://scastie.scala-lang.org/jF3rcjUfTEiRqbSO8PvgZw

import chisel3._
import chisel3.util.experimental.BoringUtils

class Foo extends Module {
  val x = IO(Input(UInt()))
  val y = IO(Input(UInt()))
  val a = IO(Output(UInt()))
  val b = IO(Output(UInt()))
 
  a := x
  b := y
}

class Bar extends Module {
  val a = IO(Input(UInt(5.W)))
  val b = IO(Input(UInt(5.W)))
  val sum = IO(Output(UInt()))
 
  val one = Module(new Foo())
  one.x := a
  one.y := b
  val two = Module(new Foo())
  two.x := a
  two.y := b
  sum := one.a + two.b
}