I'm working on a Kria board using Vivado. When I use the command val mem = SyncReadMem(64*4000, UInt(72.W)), it synthesizes to hundreds of BRAMs instead of 64 URAMs. This causes an implementation error because there are not enough BRAMs available on the board (the Kria has 144 BRAMs and 64 URAMs, both of which can be used as sequential-read memory).
To force the use of URAMs, I have to manually insert (* ram_style = "ultra" *) into the generated SystemVerilog source. How can I achieve this directly in Chisel 7?