convert *.fir file to verilog

[kf c]

Hi, everyone. Recently I want to update rocket-chip version tracked by vivado-risc-v repo. In its Makefile, it uses following command to convert generated *.fir file to verilog
```
java -Xmx12G -Xss8M  -cp target/scala-2.13/system.jar firrtl.stage.FirrtlMain -i workspace/rocket64x1/system-genesys2/RocketSystem.fir -o RocketSystem.v --compiler verilog   --annotation-file workspace/rocket64x1/system-genesys2/RocketSystem.anno.json   --custom-transforms firrtl.passes.InlineInstances   --target:fpga
```
Here, the ` target/scala-2.13/system.jar` is compiled scala source which contains rocket-chip, chisel 6.5.0 and other sources.

The problem is, when I upgrade chisel version to 6.5.0 used by rocket-chip. Above command is no longer work. The ` FirrtlMain` entry object has been removed and ` InlineInstances` also no longer exists.

What is proper way and command in chisel 6.5.0 to achieve the same effect?