Naming of modules
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Saltuk Akgül
Jan 3, 2024, 3:21:58 AMJan 3
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Hi everyone,
I want to fix names of my modules. Not instance names but module names and generated verilog file names. As suggested in the website (https://www.chisel-lang.org/docs/cookbooks/naming), I overwrite desiredName of a Queue. However, Queue generates another module and verilog file named ram_combMem_*. Is there a way to fix all module names under a module using a prefix or something?
Regards,
Saltuk
I want to fix names of my modules. Not instance names but module names and generated verilog file names. As suggested in the website (https://www.chisel-lang.org/docs/cookbooks/naming), I overwrite desiredName of a Queue. However, Queue generates another module and verilog file named ram_combMem_*. Is there a way to fix all module names under a module using a prefix or something?
Regards,
Saltuk
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