LLVM CIRCT and OpenROAD/yosys

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Øyvind Harboe

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Feb 16, 2023, 1:53:29 AM2/16/23
to chisel-users
OpenROAD (and many projects besides) use yosys.

yosys does not have full fledged System Verilog support. Also, there are other tools like Verilator that also doesn't support full System Verilog.

Are there options that I can pass to LLVM CIRCT firtool to get .v output files, so as to ensure that there are no System Verilog language features used?

It may be a bit selfish :-) but if the .sv files are compatible with Verilator, Yosys and FPGA tools like Xilinx/Quartus specifically, I have what I need.
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