Removing the "io_" prefix

[Øyvind Harboe]

Is there a way to remove the "io_" prefix for a bundle's signals in Verilog?

val io = IO(new SomeBundle)

[Bruno Ferres]

Hi,

I don't know what is your use case, but if it works for you, you could extend MultiIOModule instead of Module, allowing to define multiple IO with custom names that wouldn't start with io_ in the generated verilog

Regards,

Bruno

Le mar. 23 nov. 2021 à 09:40, Øyvind Harboe <oyvind...@gmail.com> a écrit :

Is there a way to remove the "io_" prefix for a bundle's signals in Verilog?

val io = IO(new SomeBundle)

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[Øyvind Harboe]

That requires naming the invidivudal signals, which I'd like to avoid.

I simply want to remove the "io_" prefix: this is to make the Verilog more similar to hand-coded Verilog, which is important for backend & verification engineers. It's especially important that the module interfaces are as "friendly" as possible to reduce friction when introducing Chisel usage.

[Bruno Ferres]

Then I guess something can be done just before the verilog emission transform, through some manual renaming of signals.

I don't think it's too much work as it only requires a single traversal of the IR, and could even be a "standard" transform in the framework as I guess other people could like it too.

I don't have much more insights about such implementation unfortunately.

Regards,

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[Øyvind Harboe]

io.suggestName("") will remove the "io" part of the prefix, but the io signals now have a "_" prefix, so I still need to get rid of that last "_"

I tried to modify Builder.scala in Chisel so that would not yield that "_" prefix, but I still the io prefix... That didn't do anything... I'm barking up the wrong tree... :-)

[Jack Koenig]

By the release of 3.5.0, I'd like to include a new method "FlatIO" that does what you're asking for. We'd discussed ways to accomplish this in the past, but our previous ideas all had implementation or API difficulties. Chisel 3.5 has a new feature, DataView (https://github.com/chipsalliance/chisel3/pull/1955), that makes it easier to implement this sort of feature, for example:

class Example extends Module {
  val in = FlatIO(Flipped(Decoupled(UInt(8.W))))
  val out = IO(Decoupled(UInt(8.W)))
 
  out <> in
}

would emit as:

module Example(
  input        clock,
  input        reset,
  input  [7:0] bits,
  input        valid,
  output       ready,
  input        out_ready,
  output       out_valid,
  output [7:0] out_bits
);
  assign ready = out_ready; // @[main.scala 10:7]
  assign out_valid = valid; // @[main.scala 10:7]
  assign out_bits = bits; // @[main.scala 10:7]
endmodule

And proof that this works, here's a sketch of the implementation using 3.5.0-RC1 :) : https://scastie.scala-lang.org/DOVFDr0XQNi4pWre8X7IzQ

The 1 challenge is that dynamic indexing of Vecs that are views does not currently work, so while you could copy-paste this code and use it if you're on 3.5.0-RC1 or 3.5-SNAPSHOT, it does have some current limitations.

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[Øyvind Harboe]

Nice!

I got some errors when I tried though: "Dynamic indexing of Views is not yet supported" and "Reference view_521 is not declared."

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Øyvind Harboe
+4791786146

[Øyvind Harboe]

I could get it to work for a module that didn't have any constructor arguments.

I ran into another problem though: I need FlatIO() signals to be public in Verilator.... That's supposed to be possible by generating the constraint file for Verilator... My perl scripts broke...

https://groups.google.com/g/chisel-users/c/qCGTaZmSl9c/m/vUMX_EL8BAAJ

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Øyvind Harboe
+4791786146

[Øyvind Harboe]

Hmm.... I tried to reproduce the error I had, but simply adding an argument to the constructor didn't do it: https://scastie.scala-lang.org/19GZPDHQTIedzOeC254cuQ